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Message-ID: <fea90522-dec4-4bba-be57-3a1be9e6b59c@quicinc.com>
Date: Mon, 10 Jun 2024 11:16:55 +0530
From: Devi Priya <quic_devipriy@...cinc.com>
To: Bjorn Helgaas <helgaas@...nel.org>
CC: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
<robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<andersson@...nel.org>, <konrad.dybcio@...aro.org>,
<mturquette@...libre.com>, <sboyd@...nel.org>,
<manivannan.sadhasivam@...aro.org>, <linux-arm-msm@...r.kernel.org>,
<linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH V5 6/6] PCI: qcom: Add support for IPQ9574
On 5/30/2024 10:41 PM, Bjorn Helgaas wrote:
> On Sun, May 12, 2024 at 01:58:58PM +0530, devi priya wrote:
>> The IPQ9574 platform has 4 Gen3 PCIe controllers:
>> two single-lane and two dual-lane based on SNPS core 5.70a
>
> s/4/four/ to match "two"
okay
>
>> The Qcom IP rev is 1.27.0 and Synopsys IP rev is 5.80a
>> Added a new compatible 'qcom,pcie-ipq9574' and 'ops_1_27_0'
>
> s/Added/Add/ (use imperative mood:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?id=v6.9#n94)
>
>> which reuses all the members of 'ops_2_9_0' except for the post_init
>> as the SLV_ADDR_SPACE_SIZE configuration differs between 2_9_0
>> and 1_27_0.
>
> Add periods at end of sentences. Rewrap to fill 75 columns.
okay
>
>> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
>> +{
>> + writel(SLV_ADDR_SPACE_SZ_1_27_0,
>> + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
>
> Fits on one line.
sure
>
>> + return qcom_pcie_post_init(pcie);
>> +}
>> +
>> +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
>> +{
>> + writel(SLV_ADDR_SPACE_SZ,
>> + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
>
> Fits on one line.
okay
>
>> + return qcom_pcie_post_init(pcie);
>> +}
Thanks,
Devi priya
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