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Message-ID:
<DM4PR12MB51365BA9AF19ED18E7516195C0C72@DM4PR12MB5136.namprd12.prod.outlook.com>
Date: Tue, 11 Jun 2024 13:41:38 +0000
From: Shravan Ramani <shravankr@...dia.com>
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
CC: Hans de Goede <hdegoede@...hat.com>, Vadim Pasternak <vadimp@...dia.com>,
David Thompson <davthompson@...dia.com>,
"platform-driver-x86@...r.kernel.org" <platform-driver-x86@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 4/4] Documentation/ABI: Add new sysfs fields to
sysfs-platform-mellanox-pmc
> > + Form 64-bit counter using 2 32-bit counters. This is used to combine
> > + 2 adjacent counters to form a single 64-bit counter. Each even counter
> > + is represented by a bit and setting the bit will join the corresponding
> > + even counter with the next (odd) counter. The full 64-bit value can be
> > + accessed using the same 2 counter<N> and counter<N+1> sysfs, with each
> > + of them holding the lower and upper 32 bits respectively.
>
> Okay, thanks for updating this, it's much clearer now what the intent of
> each file is. One thing that is still unclear whether both bits are
> expected to be set in count_clock when use_odd_counter is used to combine
> two counters?
When use_odd_counter is set to combine counter0 and counter1, for example, the counter
value will increment only based on what event is being monitored by counter0. So for
counting cycles with 64-bits, count_clock needs to be set for counter0. Bit1 in count_clock
as well as event1 will not matter once counter1 is joined to counter0. I will capture this as
well in the doc in the next patch when I fix the kernel version.
Thanks,
Shravan
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