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Message-ID: <20240612173213.42827-6-sebastian.reichel@collabora.com>
Date: Wed, 12 Jun 2024 19:15:45 +0200
From: Sebastian Reichel <sebastian.reichel@...labora.com>
To: Ezequiel Garcia <ezequiel@...guardiasur.com.ar>,
Philipp Zabel <p.zabel@...gutronix.de>,
Nicolas Frattaroli <frattaroli.nicolas@...il.com>,
Heiko Stuebner <heiko@...ech.de>
Cc: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Jianfeng Liu <liujianfeng1994@...il.com>,
Emmanuel Gil Peyrot <linkmauve@...kmauve.fr>,
Nicolas Dufresne <nicolas.dufresne@...labora.com>,
linux-media@...r.kernel.org,
linux-rockchip@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
kernel@...labora.com,
Hugh Cole-Baker <sigmaris@...il.com>,
Sebastian Reichel <sebastian.reichel@...labora.com>
Subject: [PATCH v5 5/5] arm64: dts: rockchip: Add VPU121 support for RK3588
From: Jianfeng Liu <liujianfeng1994@...il.com>
Enable Hantro G1 video decoder in RK3588's devicetree.
Tested with FFmpeg v4l2_request code taken from [1]
with MPEG2, H.264 and VP8 samples.
[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch
Signed-off-by: Jianfeng Liu <liujianfeng1994@...il.com>
Tested-by: Hugh Cole-Baker <sigmaris@...il.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@...labora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 9edbcfe778ca..e7e1b456b9b9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1239,6 +1239,27 @@ jpeg_enc3_mmu: iommu@...ac800 {
#iommu-cells = <0>;
};
+ vpu: video-codec@...50000 {
+ compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
+ reg = <0x0 0xfdb50000 0x0 0x800>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vpu_mmu: iommu@...50800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdb50800 0x0 0x40>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-names = "aclk", "iface";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
av1d: video-codec@...70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
--
2.43.0
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