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Message-ID: <Zmnt4RL+RcDiwurc@Asurada-Nvidia>
Date: Wed, 12 Jun 2024 11:50:09 -0700
From: Nicolin Chen <nicolinc@...dia.com>
To: Jason Gunthorpe <jgg@...dia.com>
CC: <will@...nel.org>, <robin.murphy@....com>, <joro@...tes.org>,
	<thierry.reding@...il.com>, <vdumpa@...dia.com>, <jonathanh@...dia.com>,
	<linux-kernel@...r.kernel.org>, <iommu@...ts.linux.dev>,
	<linux-arm-kernel@...ts.infradead.org>, <linux-tegra@...r.kernel.org>
Subject: Re: [PATCH v8 5/6] iommu/arm-smmu-v3: Add in-kernel support for
 NVIDIA Tegra241 (Grace) CMDQV

On Wed, Jun 12, 2024 at 09:29:25AM -0300, Jason Gunthorpe wrote:
> On Tue, May 28, 2024 at 01:09:53AM -0700, Nicolin Chen wrote:
> 
> > +/* MMIO helpers */
> > +#define REG_CMDQV(_cmdqv, _regname) \
> > +	((_cmdqv)->base + TEGRA241_CMDQV_##_regname)
> > +#define REG_VINTF(_vintf, _regname) \
> > +	((_vintf)->base + TEGRA241_VINTF_##_regname)
> > +#define REG_VCMDQ_PAGE0(_vcmdq, _regname) \
> > +	((_vcmdq)->page0 + TEGRA241_VCMDQ_##_regname)
> > +#define REG_VCMDQ_PAGE1(_vcmdq, _regname) \
> > +	((_vcmdq)->page1 + TEGRA241_VCMDQ_##_regname)
> 
> This looks OK now
> 
> I didn't see any thing else really important in this patch
> 
> Reviewed-by: Jason Gunthorpe <jgg@...dia.com>
> 
> > +static inline int cmdqv_write_config(struct tegra241_cmdqv *cmdqv, u32 regval)
> > +{
> > +	return tegra241_cmdqv_write_config(cmdqv,
> > +					   cmdqv->base + TEGRA241_CMDQV_CONFIG,
> > +					   cmdqv->base + TEGRA241_CMDQV_STATUS,
> > +					   regval, "CMDQV: ", NULL);
> 
> However it would be good to go and fix these case to use the REG_xx
> macros, I noticed several.

Will respin a v9. Thanks!

Nicolin

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