linux-kernel - Re: [PATCH 3/8] riscv: ftrace: support fastcc in Clang for WITH

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Date: Thu, 13 Jun 2024 15:36:15 -0700
From: Nathan Chancellor <nathan@...nel.org>
To: Andy Chiu <andy.chiu@...ive.com>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Alexandre Ghiti <alexghiti@...osinc.com>,
	Zong Li <zong.li@...ive.com>, Steven Rostedt <rostedt@...dmis.org>,
	Masami Hiramatsu <mhiramat@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	Nick Desaulniers <ndesaulniers@...gle.com>,
	Bill Wendling <morbo@...gle.com>,
	Justin Stitt <justinstitt@...gle.com>,
	Puranjay Mohan <puranjay@...nel.org>,
	Palmer Dabbelt <palmer@...osinc.com>,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
	linux-trace-kernel@...r.kernel.org, llvm@...ts.linux.dev,
	Evgenii Shatokhin <e.shatokhin@...ro.com>
Subject: Re: [PATCH 3/8] riscv: ftrace: support fastcc in Clang for WITH_ARGS

On Thu, Jun 13, 2024 at 03:11:08PM +0800, Andy Chiu wrote:
> Some caller-saved registers which are not defined as function arguments
> in the ABI can still be passed as arguments when the kernel is compiled
> with Clang. As a result, we must save and restore those registers to
> prevent ftrace from clobbering them.
> 
> - [1]: https://reviews.llvm.org/D68559
> Reported-by: Evgenii Shatokhin <e.shatokhin@...ro.com>
> Closes: https://lore.kernel.org/linux-riscv/7e7c7914-445d-426d-89a0-59a9199c45b1@yadro.com/
> Signed-off-by: Andy Chiu <andy.chiu@...ive.com>

Acked-by: Nathan Chancellor <nathan@...nel.org>

> ---
>  arch/riscv/include/asm/ftrace.h |  7 +++++++
>  arch/riscv/kernel/asm-offsets.c |  7 +++++++
>  arch/riscv/kernel/mcount-dyn.S  | 16 ++++++++++++++--
>  3 files changed, 28 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/ftrace.h b/arch/riscv/include/asm/ftrace.h
> index 9eb31a7ea0aa..5f81c53dbfd9 100644
> --- a/arch/riscv/include/asm/ftrace.h
> +++ b/arch/riscv/include/asm/ftrace.h
> @@ -144,6 +144,13 @@ struct ftrace_regs {
>  			unsigned long a5;
>  			unsigned long a6;
>  			unsigned long a7;
> +#ifdef CONFIG_CC_IS_CLANG
> +			unsigned long t2;
> +			unsigned long t3;
> +			unsigned long t4;
> +			unsigned long t5;
> +			unsigned long t6;
> +#endif
>  		};
>  	};
>  };
> diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c
> index b09ca5f944f7..db5a26fcc9ae 100644
> --- a/arch/riscv/kernel/asm-offsets.c
> +++ b/arch/riscv/kernel/asm-offsets.c
> @@ -497,6 +497,13 @@ void asm_offsets(void)
>  	DEFINE(FREGS_SP,	    offsetof(struct ftrace_regs, sp));
>  	DEFINE(FREGS_S0,	    offsetof(struct ftrace_regs, s0));
>  	DEFINE(FREGS_T1,	    offsetof(struct ftrace_regs, t1));
> +#ifdef CONFIG_CC_IS_CLANG
> +	DEFINE(FREGS_T2,	    offsetof(struct ftrace_regs, t2));
> +	DEFINE(FREGS_T3,	    offsetof(struct ftrace_regs, t3));
> +	DEFINE(FREGS_T4,	    offsetof(struct ftrace_regs, t4));
> +	DEFINE(FREGS_T5,	    offsetof(struct ftrace_regs, t5));
> +	DEFINE(FREGS_T6,	    offsetof(struct ftrace_regs, t6));
> +#endif
>  	DEFINE(FREGS_A0,	    offsetof(struct ftrace_regs, a0));
>  	DEFINE(FREGS_A1,	    offsetof(struct ftrace_regs, a1));
>  	DEFINE(FREGS_A2,	    offsetof(struct ftrace_regs, a2));
> diff --git a/arch/riscv/kernel/mcount-dyn.S b/arch/riscv/kernel/mcount-dyn.S
> index 745dd4c4a69c..e988bd26b28b 100644
> --- a/arch/riscv/kernel/mcount-dyn.S
> +++ b/arch/riscv/kernel/mcount-dyn.S
> @@ -96,7 +96,13 @@
>  	REG_S	x8,  FREGS_S0(sp)
>  #endif
>  	REG_S	x6,  FREGS_T1(sp)
> -
> +#ifdef CONFIG_CC_IS_CLANG
> +	REG_S	x7,  FREGS_T2(sp)
> +	REG_S	x28, FREGS_T3(sp)
> +	REG_S	x29, FREGS_T4(sp)
> +	REG_S	x30, FREGS_T5(sp)
> +	REG_S	x31, FREGS_T6(sp)
> +#endif
>  	// save the arguments
>  	REG_S	x10, FREGS_A0(sp)
>  	REG_S	x11, FREGS_A1(sp)
> @@ -115,7 +121,13 @@
>  	REG_L	x8, FREGS_S0(sp)
>  #endif
>  	REG_L	x6,  FREGS_T1(sp)
> -
> +#ifdef CONFIG_CC_IS_CLANG
> +	REG_L	x7,  FREGS_T2(sp)
> +	REG_L	x28, FREGS_T3(sp)
> +	REG_L	x29, FREGS_T4(sp)
> +	REG_L	x30, FREGS_T5(sp)
> +	REG_L	x31, FREGS_T6(sp)
> +#endif
>  	// restore the arguments
>  	REG_L	x10, FREGS_A0(sp)
>  	REG_L	x11, FREGS_A1(sp)
> 
> -- 
> 2.43.0
>