lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Thu, 13 Jun 2024 09:26:01 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: daire.mcnamara@...rochip.com, linux-pci@...r.kernel.org,
 devicetree@...r.kernel.org
Cc: conor.dooley@...rochip.com, lpieralisi@...nel.org, kw@...ux.com,
 robh@...nel.org, bhelgaas@...gle.com, linux-kernel@...r.kernel.org,
 linux-riscv@...ts.infradead.org, krzk+dt@...nel.org, conor+dt@...nel.org
Subject: Re: [PATCH v3 3/3] dt-bindings: PCI: microchip,pcie-host: allow
 dma-noncoherent

On 12/06/2024 13:22, daire.mcnamara@...rochip.com wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> PolarFire SoC may be configured in a way that requires non-coherent DMA
> handling. On RISC-V, buses are coherent by default & the dma-noncoherent
> property is required to denote buses or devices that are non-coherent.
> 
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> Signed-off-by: Daire McNamara <daire.mcnamara@...rochip.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>

Best regards,
Krzysztof


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ