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Message-Id: <20240614230146.3783221-21-irogers@google.com>
Date: Fri, 14 Jun 2024 16:01:28 -0700
From: Ian Rogers <irogers@...gle.com>
To: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>, Jiri Olsa <jolsa@...nel.org>,
Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>,
Kan Liang <kan.liang@...ux.intel.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org
Cc: Weilin Wang <weilin.wang@...el.com>, Caleb Biggers <caleb.biggers@...el.com>
Subject: [PATCH v1 20/37] perf vendor events: Update jaketown metrics add
event counter information
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
The TMA 4.8 information was updated in:
https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9a5736
Co-authored-by: Weilin Wang <weilin.wang@...el.com>
Co-authored-by: Caleb Biggers <caleb.biggers@...el.com>
Signed-off-by: Ian Rogers <irogers@...gle.com>
---
.../pmu-events/arch/x86/jaketown/cache.json | 123 +++++++++++
.../pmu-events/arch/x86/jaketown/counter.json | 52 +++++
.../arch/x86/jaketown/floating-point.json | 15 ++
.../arch/x86/jaketown/frontend.json | 32 +++
.../arch/x86/jaketown/jkt-metrics.json | 24 +-
.../pmu-events/arch/x86/jaketown/memory.json | 35 +++
.../arch/x86/jaketown/metricgroups.json | 11 +
.../pmu-events/arch/x86/jaketown/other.json | 6 +
.../arch/x86/jaketown/pipeline.json | 127 +++++++++++
.../arch/x86/jaketown/uncore-cache.json | 205 +++++++++++++++++
.../x86/jaketown/uncore-interconnect.json | 207 ++++++++++++++++++
.../arch/x86/jaketown/uncore-io.json | 36 +++
.../arch/x86/jaketown/uncore-memory.json | 51 +++++
.../arch/x86/jaketown/uncore-power.json | 39 ++++
.../arch/x86/jaketown/virtual-memory.json | 16 ++
15 files changed, 967 insertions(+), 12 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/jaketown/counter.json
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/cache.json b/tools/perf/pmu-events/arch/x86/jaketown/cache.json
index b9769d39940c..ab3713c469e3 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/cache.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/cache.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Allocated L1D data cache lines in M state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.ALLOCATED_IN_M",
"SampleAfterValue": "2000003",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.ALL_M_REPLACEMENT",
"SampleAfterValue": "2000003",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "L1D data cache lines in M state evicted due to replacement.",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.EVICTION",
"SampleAfterValue": "2000003",
@@ -22,6 +25,7 @@
},
{
"BriefDescription": "L1D data line replacements.",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.",
@@ -30,6 +34,7 @@
},
{
"BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xBF",
"EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES",
@@ -38,6 +43,7 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@@ -46,6 +52,7 @@
},
{
"BriefDescription": "L1D miss outstanding duration in cycles.",
+ "Counter": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"SampleAfterValue": "2000003",
@@ -53,6 +60,7 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
+ "Counter": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -62,6 +70,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
+ "Counter": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -70,6 +79,7 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.ALL",
"SampleAfterValue": "200003",
@@ -77,6 +87,7 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_E",
"SampleAfterValue": "200003",
@@ -84,6 +95,7 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_M",
"SampleAfterValue": "200003",
@@ -91,6 +103,7 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_S",
"SampleAfterValue": "200003",
@@ -98,6 +111,7 @@
},
{
"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.MISS",
"SampleAfterValue": "200003",
@@ -105,6 +119,7 @@
},
{
"BriefDescription": "L2 cache lines filling L2.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
@@ -113,6 +128,7 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"SampleAfterValue": "100003",
@@ -120,6 +136,7 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"SampleAfterValue": "100003",
@@ -127,6 +144,7 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"SampleAfterValue": "100003",
@@ -134,6 +152,7 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100003",
@@ -141,6 +160,7 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by demand.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100003",
@@ -148,6 +168,7 @@
},
{
"BriefDescription": "Dirty L2 cache lines filling the L2.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DIRTY_ALL",
"SampleAfterValue": "100003",
@@ -155,6 +176,7 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_CLEAN",
"SampleAfterValue": "100003",
@@ -162,6 +184,7 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_DIRTY",
"SampleAfterValue": "100003",
@@ -169,6 +192,7 @@
},
{
"BriefDescription": "L2 code requests.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"SampleAfterValue": "200003",
@@ -176,6 +200,7 @@
},
{
"BriefDescription": "Demand Data Read requests.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"SampleAfterValue": "200003",
@@ -183,6 +208,7 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"SampleAfterValue": "200003",
@@ -190,6 +216,7 @@
},
{
"BriefDescription": "RFO requests to L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"SampleAfterValue": "200003",
@@ -197,6 +224,7 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
@@ -204,6 +232,7 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue": "200003",
@@ -211,6 +240,7 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"SampleAfterValue": "200003",
@@ -218,6 +248,7 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT",
"SampleAfterValue": "200003",
@@ -225,6 +256,7 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS",
"SampleAfterValue": "200003",
@@ -232,6 +264,7 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003",
@@ -239,6 +272,7 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200003",
@@ -246,6 +280,7 @@
},
{
"BriefDescription": "RFOs that access cache lines in any state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.ALL",
"SampleAfterValue": "200003",
@@ -253,6 +288,7 @@
},
{
"BriefDescription": "RFOs that hit cache lines in E state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.HIT_E",
"SampleAfterValue": "200003",
@@ -260,6 +296,7 @@
},
{
"BriefDescription": "RFOs that hit cache lines in M state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
"SampleAfterValue": "200003",
@@ -267,6 +304,7 @@
},
{
"BriefDescription": "RFOs that miss cache lines.",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.MISS",
"SampleAfterValue": "200003",
@@ -274,6 +312,7 @@
},
{
"BriefDescription": "L2 or LLC HW prefetches that access L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"SampleAfterValue": "200003",
@@ -281,6 +320,7 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"SampleAfterValue": "200003",
@@ -288,6 +328,7 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"SampleAfterValue": "200003",
@@ -295,6 +336,7 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"SampleAfterValue": "200003",
@@ -302,6 +344,7 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"SampleAfterValue": "200003",
@@ -309,6 +352,7 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"SampleAfterValue": "200003",
@@ -316,6 +360,7 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"SampleAfterValue": "200003",
@@ -323,6 +368,7 @@
},
{
"BriefDescription": "RFO requests that access L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"SampleAfterValue": "200003",
@@ -330,6 +376,7 @@
},
{
"BriefDescription": "Cycles when L1D is locked.",
+ "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"SampleAfterValue": "2000003",
@@ -337,6 +384,7 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed LLC.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100003",
@@ -344,6 +392,7 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to LLC.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "100003",
@@ -351,6 +400,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.",
@@ -359,6 +409,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.",
@@ -367,6 +418,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
"SampleAfterValue": "20011",
@@ -374,6 +426,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
"SampleAfterValue": "100003",
@@ -381,6 +434,7 @@
},
{
"BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
"SampleAfterValue": "100007",
@@ -388,6 +442,7 @@
},
{
"BriefDescription": "Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",
"SampleAfterValue": "100007",
@@ -395,6 +450,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -403,6 +459,7 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1",
@@ -411,6 +468,7 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
@@ -419,6 +477,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required.",
@@ -427,6 +486,7 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
"SampleAfterValue": "100007",
@@ -434,6 +494,7 @@
},
{
"BriefDescription": "All retired load uops.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
@@ -443,6 +504,7 @@
},
{
"BriefDescription": "All retired store uops.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
@@ -452,6 +514,7 @@
},
{
"BriefDescription": "Retired load uops with locked access.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
@@ -460,6 +523,7 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
@@ -469,6 +533,7 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "1",
@@ -478,6 +543,7 @@
},
{
"BriefDescription": "Retired load uops that miss the STLB.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
@@ -486,6 +552,7 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"PEBS": "1",
@@ -494,6 +561,7 @@
},
{
"BriefDescription": "Demand and prefetch data reads.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"SampleAfterValue": "100003",
@@ -501,6 +569,7 @@
},
{
"BriefDescription": "Cacheable and non-cacheable code read requests.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"SampleAfterValue": "100003",
@@ -508,6 +577,7 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"SampleAfterValue": "100003",
@@ -515,6 +585,7 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"SampleAfterValue": "100003",
@@ -522,6 +593,7 @@
},
{
"BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"SampleAfterValue": "2000003",
@@ -529,6 +601,7 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"SampleAfterValue": "2000003",
@@ -536,6 +609,7 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -544,6 +618,7 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -552,6 +627,7 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -560,6 +636,7 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"SampleAfterValue": "2000003",
@@ -567,6 +644,7 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
+ "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6",
@@ -575,6 +653,7 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"SampleAfterValue": "2000003",
@@ -582,6 +661,7 @@
},
{
"BriefDescription": "Counts all demand & prefetch data reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -591,6 +671,7 @@
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
@@ -600,6 +681,7 @@
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -609,6 +691,7 @@
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -618,6 +701,7 @@
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -627,6 +711,7 @@
},
{
"BriefDescription": "Counts all prefetch data reads that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -636,6 +721,7 @@
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
@@ -645,6 +731,7 @@
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -654,6 +741,7 @@
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -663,6 +751,7 @@
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -672,6 +761,7 @@
},
{
"BriefDescription": "Counts all data/code/rfo references (demand & prefetch)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -681,6 +771,7 @@
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -690,6 +781,7 @@
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
@@ -699,6 +791,7 @@
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -708,6 +801,7 @@
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -717,6 +811,7 @@
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -726,6 +821,7 @@
},
{
"BriefDescription": "Counts all demand & prefetch prefetch RFOs",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -735,6 +831,7 @@
},
{
"BriefDescription": "Counts all writebacks from the core to the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -744,6 +841,7 @@
},
{
"BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -753,6 +851,7 @@
},
{
"BriefDescription": "Counts all demand code reads that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -762,6 +861,7 @@
},
{
"BriefDescription": "Counts all demand data reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -771,6 +871,7 @@
},
{
"BriefDescription": "Counts all demand data reads that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -780,6 +881,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
@@ -789,6 +891,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -798,6 +901,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -807,6 +911,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -816,6 +921,7 @@
},
{
"BriefDescription": "Counts all demand rfo's",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -825,6 +931,7 @@
},
{
"BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
"MSRIndex": "0x1a6,0x1a7",
@@ -834,6 +941,7 @@
},
{
"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
"MSRIndex": "0x1a6,0x1a7",
@@ -843,6 +951,7 @@
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -852,6 +961,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -861,6 +971,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
@@ -870,6 +981,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -879,6 +991,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -888,6 +1001,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -897,6 +1011,7 @@
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -906,6 +1021,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -915,6 +1031,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
@@ -924,6 +1041,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -933,6 +1051,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -942,6 +1061,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -951,6 +1071,7 @@
},
{
"BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -960,6 +1081,7 @@
},
{
"BriefDescription": "Counts non-temporal stores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -969,6 +1091,7 @@
},
{
"BriefDescription": "Split locks in SQ.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/counter.json b/tools/perf/pmu-events/arch/x86/jaketown/counter.json
new file mode 100644
index 000000000000..fac24dfeb23f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/jaketown/counter.json
@@ -0,0 +1,52 @@
+[
+ {
+ "Unit": "core",
+ "CountersNumFixed": "3",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "CBOX",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "PCU",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "UBOX",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "2"
+ },
+ {
+ "Unit": "QPI",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "R3QPI",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "3"
+ },
+ {
+ "Unit": "R2PCIe",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "HA",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "iMC",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "IRP",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "2"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json
index 79e8f403c426..8b570829e2e0 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Cycles with any input/output SSE or FP assist.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values.",
+ "Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"SampleAfterValue": "100003",
@@ -16,6 +18,7 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values.",
+ "Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"SampleAfterValue": "100003",
@@ -23,6 +26,7 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
+ "Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"SampleAfterValue": "100003",
@@ -30,6 +34,7 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
+ "Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"SampleAfterValue": "100003",
@@ -37,6 +42,7 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@@ -44,6 +50,7 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"SampleAfterValue": "2000003",
@@ -51,6 +58,7 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
@@ -58,6 +66,7 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"SampleAfterValue": "2000003",
@@ -65,6 +74,7 @@
},
{
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000003",
@@ -72,6 +82,7 @@
},
{
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"SampleAfterValue": "100003",
@@ -79,6 +90,7 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
@@ -86,6 +98,7 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
@@ -93,6 +106,7 @@
},
{
"BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@@ -100,6 +114,7 @@
},
{
"BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json
index 754ee2749485..3cb468da7011 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"SampleAfterValue": "2000003",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
@@ -23,6 +26,7 @@
},
{
"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "DSB_FILL.ALL_CANCEL",
"SampleAfterValue": "2000003",
@@ -30,6 +34,7 @@
},
{
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
"SampleAfterValue": "2000003",
@@ -37,6 +42,7 @@
},
{
"BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "DSB_FILL.OTHER_CANCEL",
"SampleAfterValue": "2000003",
@@ -44,6 +50,7 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
@@ -51,6 +58,7 @@
},
{
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
@@ -59,6 +67,7 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
+ "Counter": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -67,6 +76,7 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -75,6 +85,7 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops.",
+ "Counter": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -83,6 +94,7 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -91,6 +103,7 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -99,6 +112,7 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"SampleAfterValue": "2000003",
@@ -106,6 +120,7 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"SampleAfterValue": "2000003",
@@ -113,6 +128,7 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"SampleAfterValue": "2000003",
@@ -120,6 +136,7 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -128,6 +145,7 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"SampleAfterValue": "2000003",
@@ -135,6 +153,7 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -144,6 +163,7 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -152,6 +172,7 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -161,6 +182,7 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"SampleAfterValue": "2000003",
@@ -168,6 +190,7 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"SampleAfterValue": "2000003",
@@ -175,6 +198,7 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -184,6 +208,7 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"SampleAfterValue": "2000003",
@@ -191,6 +216,7 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
@@ -199,6 +225,7 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
+ "Counter": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -207,6 +234,7 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -216,6 +244,7 @@
},
{
"BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
+ "Counter": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
@@ -225,6 +254,7 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
+ "Counter": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -233,6 +263,7 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
+ "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -241,6 +272,7 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
index fc8c3f785be1..f8c18741b360 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
@@ -73,7 +73,7 @@
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
"MetricConstraint": "NO_GROUP_EVENTS_NMI",
"MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
- "MetricGroup": "TmaL1;TopdownL1;tma_L1_group",
+ "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group",
"MetricName": "tma_backend_bound",
"MetricThreshold": "tma_backend_bound > 0.2",
"MetricgroupNoGroup": "TopdownL1",
@@ -94,7 +94,7 @@
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
"MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
- "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
+ "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
"MetricName": "tma_branch_mispredicts",
"MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15",
"MetricgroupNoGroup": "TopdownL2",
@@ -124,7 +124,7 @@
{
"BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
"MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks",
- "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group",
"MetricName": "tma_divider",
"MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
"PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS",
@@ -152,7 +152,7 @@
{
"BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
"MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group",
+ "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group",
"MetricName": "tma_dtlb_load",
"MetricThreshold": "tma_dtlb_load > 0.1",
"PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store",
@@ -226,7 +226,7 @@
{
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots",
- "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group",
+ "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group",
"MetricName": "tma_frontend_bound",
"MetricThreshold": "tma_frontend_bound > 0.15",
"MetricgroupNoGroup": "TopdownL1",
@@ -296,13 +296,13 @@
},
{
"BriefDescription": "Average CPU Utilization (percentage)",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online",
"MetricGroup": "HPC;Summary",
"MetricName": "tma_info_system_cpu_utilization"
},
{
"BriefDescription": "Average number of utilized CPUs",
- "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "Summary",
"MetricName": "tma_info_system_cpus_utilized"
},
@@ -419,7 +419,7 @@
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
"MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_thread_clks",
- "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
"MetricName": "tma_itlb_misses",
"MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED",
@@ -458,7 +458,7 @@
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
"MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
- "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn",
+ "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn",
"MetricName": "tma_machine_clears",
"MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15",
"MetricgroupNoGroup": "TopdownL2",
@@ -468,7 +468,7 @@
{
"BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM)",
"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@...CORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / tma_info_thread_clks",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW",
+ "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW",
"MetricName": "tma_mem_bandwidth",
"MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_info_system_dram_bw_use",
@@ -477,7 +477,7 @@
{
"BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM)",
"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat",
+ "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat",
"MetricName": "tma_mem_latency",
"MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: ",
@@ -525,7 +525,7 @@
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots",
- "MetricGroup": "TmaL1;TopdownL1;tma_L1_group",
+ "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group",
"MetricName": "tma_retiring",
"MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1",
"MetricgroupNoGroup": "TopdownL1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/memory.json b/tools/perf/pmu-events/arch/x86/jaketown/memory.json
index a71e630fd030..41200f0e0df6 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/memory.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Loads with latency value being above 128.",
+ "Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
@@ -19,6 +21,7 @@
},
{
"BriefDescription": "Loads with latency value being above 16.",
+ "Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
@@ -29,6 +32,7 @@
},
{
"BriefDescription": "Loads with latency value being above 256.",
+ "Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
@@ -39,6 +43,7 @@
},
{
"BriefDescription": "Loads with latency value being above 32.",
+ "Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
@@ -49,6 +54,7 @@
},
{
"BriefDescription": "Loads with latency value being above 4 .",
+ "Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
@@ -59,6 +65,7 @@
},
{
"BriefDescription": "Loads with latency value being above 512.",
+ "Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
@@ -69,6 +76,7 @@
},
{
"BriefDescription": "Loads with latency value being above 64.",
+ "Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
@@ -79,6 +87,7 @@
},
{
"BriefDescription": "Loads with latency value being above 8.",
+ "Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
@@ -89,6 +98,7 @@
},
{
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
+ "Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
"PEBS": "2",
@@ -97,6 +107,7 @@
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"SampleAfterValue": "2000003",
@@ -104,6 +115,7 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"SampleAfterValue": "2000003",
@@ -111,6 +123,7 @@
},
{
"BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -120,6 +133,7 @@
},
{
"BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -129,6 +143,7 @@
},
{
"BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
@@ -138,6 +153,7 @@
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -147,6 +163,7 @@
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -156,6 +173,7 @@
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -165,6 +183,7 @@
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -174,6 +193,7 @@
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
@@ -183,6 +203,7 @@
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -192,6 +213,7 @@
},
{
"BriefDescription": "Counts demand data reads that miss in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -201,6 +223,7 @@
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -210,6 +233,7 @@
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -219,6 +243,7 @@
},
{
"BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -228,6 +253,7 @@
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
@@ -237,6 +263,7 @@
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -246,6 +273,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -255,6 +283,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -264,6 +293,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -273,6 +303,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -282,6 +313,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -291,6 +323,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
@@ -300,6 +333,7 @@
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -309,6 +343,7 @@
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/metricgroups.json b/tools/perf/pmu-events/arch/x86/jaketown/metricgroups.json
index a2c27794c0d8..7dc7eb0d3dd3 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/metricgroups.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/metricgroups.json
@@ -5,7 +5,18 @@
"BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/other.json b/tools/perf/pmu-events/arch/x86/jaketown/other.json
index 9f96121baef8..42692fa24b6c 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/other.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/other.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"SampleAfterValue": "2000003",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
@@ -24,6 +27,7 @@
},
{
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
+ "Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "HW_PRE_REQ.DL1_MISS",
"SampleAfterValue": "2000003",
@@ -31,6 +35,7 @@
},
{
"BriefDescription": "Valid instructions written to IQ per cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
"SampleAfterValue": "2000003",
@@ -38,6 +43,7 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
+ "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
index d0edfdec9f01..ca0694c33de1 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "AGU_BYPASS_CANCEL.COUNT",
"SampleAfterValue": "100003",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Divide operations executed.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -18,6 +20,7 @@
},
{
"BriefDescription": "Cycles when divider is busy executing divide operations.",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"SampleAfterValue": "2000003",
@@ -25,6 +28,7 @@
},
{
"BriefDescription": "Speculative and retired branches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"SampleAfterValue": "200003",
@@ -32,6 +36,7 @@
},
{
"BriefDescription": "Speculative and retired macro-conditional branches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -39,6 +44,7 @@
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"SampleAfterValue": "200003",
@@ -46,6 +52,7 @@
},
{
"BriefDescription": "Speculative and retired direct near calls.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -53,6 +60,7 @@
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -60,6 +68,7 @@
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -67,6 +76,7 @@
},
{
"BriefDescription": "Not taken macro-conditional branches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -74,6 +84,7 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -81,6 +92,7 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"SampleAfterValue": "200003",
@@ -88,6 +100,7 @@
},
{
"BriefDescription": "Taken speculative and retired direct near calls.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -95,6 +108,7 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -102,6 +116,7 @@
},
{
"BriefDescription": "Taken speculative and retired indirect calls.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -109,6 +124,7 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -116,12 +132,14 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -130,6 +148,7 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -138,6 +157,7 @@
},
{
"BriefDescription": "Far branch instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"SampleAfterValue": "100007",
@@ -145,6 +165,7 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -153,6 +174,7 @@
},
{
"BriefDescription": "Return instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -161,6 +183,7 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -169,6 +192,7 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"SampleAfterValue": "400009",
@@ -176,6 +200,7 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"SampleAfterValue": "200003",
@@ -183,6 +208,7 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -190,6 +216,7 @@
},
{
"BriefDescription": "Speculative and retired mispredicted direct near calls.",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -197,6 +224,7 @@
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -204,6 +232,7 @@
},
{
"BriefDescription": "Speculative mispredicted indirect branches",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT",
"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).",
@@ -212,6 +241,7 @@
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -219,6 +249,7 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -226,6 +257,7 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted direct near calls.",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -233,6 +265,7 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -240,6 +273,7 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -247,6 +281,7 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"SampleAfterValue": "200003",
@@ -254,12 +289,14 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
+ "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -268,6 +305,7 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -276,6 +314,7 @@
},
{
"BriefDescription": "Direct and indirect mispredicted near call instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -284,6 +323,7 @@
},
{
"BriefDescription": "Mispredicted not taken branch instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NOT_TAKEN",
"PEBS": "1",
@@ -292,6 +332,7 @@
},
{
"BriefDescription": "Mispredicted taken branch instructions retired.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.TAKEN",
"PEBS": "1",
@@ -300,6 +341,7 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -307,6 +349,7 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"SampleAfterValue": "2000003",
@@ -315,6 +358,7 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -322,6 +366,7 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -329,6 +374,7 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
+ "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -336,6 +382,7 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"SampleAfterValue": "2000003",
@@ -344,6 +391,7 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -351,6 +399,7 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state.",
+ "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -359,12 +408,14 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
+ "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000003"
@@ -372,12 +423,14 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
+ "Counter": "2",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -386,6 +439,7 @@
},
{
"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -394,6 +448,7 @@
},
{
"BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",
+ "Counter": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",
@@ -402,6 +457,7 @@
},
{
"BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
+ "Counter": "2",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -410,6 +466,7 @@
},
{
"BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",
+ "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -418,6 +475,7 @@
},
{
"BriefDescription": "Stall cycles because IQ is full.",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000003",
@@ -425,6 +483,7 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000003",
@@ -432,6 +491,7 @@
},
{
"BriefDescription": "Instructions retired from execution.",
+ "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
"SampleAfterValue": "2000003",
@@ -439,12 +499,14 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Instructions retired. (Precise Event - PEBS).",
+ "Counter": "1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "2",
@@ -453,6 +515,7 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.",
+ "Counter": "0,1,2,3",
"EventCode": "0x0D",
"EventName": "INT_MISC.RAT_STALL_CYCLES",
"SampleAfterValue": "2000003",
@@ -460,6 +523,7 @@
},
{
"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -469,6 +533,7 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -477,6 +542,7 @@
},
{
"BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x0D",
@@ -486,6 +552,7 @@
},
{
"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"SampleAfterValue": "100003",
@@ -493,6 +560,7 @@
},
{
"BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"SampleAfterValue": "100003",
@@ -500,6 +568,7 @@
},
{
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"SampleAfterValue": "100003",
@@ -507,6 +576,7 @@
},
{
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
@@ -515,6 +585,7 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare.",
+ "Counter": "0,1,2,3",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.",
@@ -523,6 +594,7 @@
},
{
"BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",
+ "Counter": "0,1,2,3",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",
"SampleAfterValue": "100003",
@@ -530,6 +602,7 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF",
"SampleAfterValue": "100003",
@@ -537,6 +610,7 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"SampleAfterValue": "100003",
@@ -544,6 +618,7 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
+ "Counter": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -552,6 +627,7 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -560,6 +636,7 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003",
@@ -567,6 +644,7 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
@@ -576,6 +654,7 @@
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
@@ -584,6 +663,7 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.",
@@ -592,6 +672,7 @@
},
{
"BriefDescription": "Retired instructions experiencing ITLB misses.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED",
"SampleAfterValue": "100003",
@@ -599,6 +680,7 @@
},
{
"BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP",
"SampleAfterValue": "2000003",
@@ -606,6 +688,7 @@
},
{
"BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES",
@@ -615,6 +698,7 @@
},
{
"BriefDescription": "Multiply packed/scalar single precision uops allocated.",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",
"SampleAfterValue": "2000003",
@@ -622,6 +706,7 @@
},
{
"BriefDescription": "Cycles with at least one slow LEA uop being allocated.",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",
"PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",
@@ -630,6 +715,7 @@
},
{
"BriefDescription": "Resource-related stall cycles.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000003",
@@ -637,6 +723,7 @@
},
{
"BriefDescription": "Counts the cycles of stall due to lack of load buffers.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LB",
"SampleAfterValue": "2000003",
@@ -644,6 +731,7 @@
},
{
"BriefDescription": "Resource stalls due to load or store buffers all being in use.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LB_SB",
"SampleAfterValue": "2000003",
@@ -651,6 +739,7 @@
},
{
"BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MEM_RS",
"SampleAfterValue": "2000003",
@@ -658,6 +747,7 @@
},
{
"BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OOO_RSRC",
"SampleAfterValue": "2000003",
@@ -665,6 +755,7 @@
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003",
@@ -672,6 +763,7 @@
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
@@ -679,6 +771,7 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"SampleAfterValue": "2000003",
@@ -686,6 +779,7 @@
},
{
"BriefDescription": "Cycles with either free list is empty.",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY",
"SampleAfterValue": "2000003",
@@ -693,6 +787,7 @@
},
{
"BriefDescription": "Resource stalls2 control structures full for physical registers.",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL",
"SampleAfterValue": "2000003",
@@ -700,6 +795,7 @@
},
{
"BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.BOB_FULL",
"SampleAfterValue": "2000003",
@@ -707,6 +803,7 @@
},
{
"BriefDescription": "Resource stalls out of order resources full.",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.OOO_RSRC",
"SampleAfterValue": "2000003",
@@ -714,6 +811,7 @@
},
{
"BriefDescription": "Count cases of saving new LBR.",
+ "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"SampleAfterValue": "2000003",
@@ -721,6 +819,7 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"SampleAfterValue": "2000003",
@@ -728,6 +827,7 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -738,6 +838,7 @@
},
{
"BriefDescription": "Uops dispatched from any thread.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_DISPATCHED.CORE",
"SampleAfterValue": "2000003",
@@ -745,6 +846,7 @@
},
{
"BriefDescription": "Uops dispatched per thread.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_DISPATCHED.THREAD",
"SampleAfterValue": "2000003",
@@ -752,6 +854,7 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"SampleAfterValue": "2000003",
@@ -760,6 +863,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 0.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
@@ -767,6 +871,7 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 1.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"SampleAfterValue": "2000003",
@@ -775,6 +880,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 1.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
@@ -782,6 +888,7 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"SampleAfterValue": "2000003",
@@ -790,6 +897,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
@@ -797,6 +905,7 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"SampleAfterValue": "2000003",
@@ -805,6 +914,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
@@ -812,6 +922,7 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 4.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"SampleAfterValue": "2000003",
@@ -820,6 +931,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 4.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
@@ -827,6 +939,7 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 5.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"SampleAfterValue": "2000003",
@@ -835,6 +948,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 5.",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
@@ -842,6 +956,7 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -850,6 +965,7 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -858,6 +974,7 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -866,6 +983,7 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -874,6 +992,7 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1",
@@ -882,6 +1001,7 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).",
+ "Counter": "0,1,2,3",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
@@ -891,6 +1011,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -900,6 +1021,7 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -909,6 +1031,7 @@
},
{
"BriefDescription": "Actually retired uops.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
@@ -918,6 +1041,7 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -927,6 +1051,7 @@
},
{
"BriefDescription": "Retirement slots used.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -936,6 +1061,7 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -945,6 +1071,7 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
+ "Counter": "0,1,2,3",
"CounterMask": "10",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json
index 63395e7ee0ce..8508becead5a 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json
@@ -1,12 +1,14 @@
[
{
"BriefDescription": "Uncore Clocks",
+ "Counter": "0,1,2,3",
"EventName": "UNC_C_CLOCKTICKS",
"PerPkg": "1",
"Unit": "CBOX"
},
{
"BriefDescription": "Counter 0 Occupancy",
+ "Counter": "1,2,3",
"EventCode": "0x1f",
"EventName": "UNC_C_COUNTER0_OCCUPANCY",
"PerPkg": "1",
@@ -14,6 +16,7 @@
"Unit": "CBOX"
},
{
+ "Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_C_ISMQ_DRD_MISS_OCC",
"PerPkg": "1",
@@ -21,6 +24,7 @@
},
{
"BriefDescription": "Cache Lookups; Data Read Request",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
@@ -30,6 +34,7 @@
},
{
"BriefDescription": "Cache Lookups; RTID",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.NID",
"PerPkg": "1",
@@ -39,6 +44,7 @@
},
{
"BriefDescription": "Cache Lookups; External Snoop Request",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
@@ -48,6 +54,7 @@
},
{
"BriefDescription": "Cache Lookups; Write Requests",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.WRITE",
"PerPkg": "1",
@@ -57,6 +64,7 @@
},
{
"BriefDescription": "Lines Victimized; Lines in E state",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
@@ -66,6 +74,7 @@
},
{
"BriefDescription": "Lines Victimized",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.MISS",
"PerPkg": "1",
@@ -75,6 +84,7 @@
},
{
"BriefDescription": "Lines Victimized; Lines in M state",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
@@ -84,6 +94,7 @@
},
{
"BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.NID",
"PerPkg": "1",
@@ -93,6 +104,7 @@
},
{
"BriefDescription": "Lines Victimized; Lines in S State",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.S_STATE",
"PerPkg": "1",
@@ -102,6 +114,7 @@
},
{
"BriefDescription": "Cbo Misc; RFO HitS",
+ "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RFO_HIT_S",
"PerPkg": "1",
@@ -111,6 +124,7 @@
},
{
"BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+ "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
@@ -120,6 +134,7 @@
},
{
"BriefDescription": "Cbo Misc",
+ "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.STARTED",
"PerPkg": "1",
@@ -129,6 +144,7 @@
},
{
"BriefDescription": "Cbo Misc; Write Combining Aliasing",
+ "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.WC_ALIASING",
"PerPkg": "1",
@@ -138,6 +154,7 @@
},
{
"BriefDescription": "AD Ring In Use; Down and Even",
+ "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
"PerPkg": "1",
@@ -147,6 +164,7 @@
},
{
"BriefDescription": "AD Ring In Use; Down and Odd",
+ "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
"PerPkg": "1",
@@ -156,6 +174,7 @@
},
{
"BriefDescription": "AD Ring In Use; Up and Even",
+ "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.UP_EVEN",
"PerPkg": "1",
@@ -165,6 +184,7 @@
},
{
"BriefDescription": "AD Ring In Use; Up and Odd",
+ "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.UP_ODD",
"PerPkg": "1",
@@ -174,6 +194,7 @@
},
{
"BriefDescription": "AK Ring In Use; Down and Even",
+ "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
@@ -183,6 +204,7 @@
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
+ "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
@@ -192,6 +214,7 @@
},
{
"BriefDescription": "AK Ring In Use; Up and Even",
+ "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
@@ -201,6 +224,7 @@
},
{
"BriefDescription": "AK Ring In Use; Up and Odd",
+ "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.UP_ODD",
"PerPkg": "1",
@@ -210,6 +234,7 @@
},
{
"BriefDescription": "BL Ring in Use; Down and Even",
+ "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
@@ -219,6 +244,7 @@
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
+ "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
@@ -228,6 +254,7 @@
},
{
"BriefDescription": "BL Ring in Use; Up and Even",
+ "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.UP_EVEN",
"PerPkg": "1",
@@ -237,6 +264,7 @@
},
{
"BriefDescription": "BL Ring in Use; Up and Odd",
+ "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.UP_ODD",
"PerPkg": "1",
@@ -246,6 +274,7 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AK_CORE",
"PerPkg": "1",
@@ -254,6 +283,7 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.BL_CORE",
"PerPkg": "1",
@@ -262,6 +292,7 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.IV_CORE",
"PerPkg": "1",
@@ -270,6 +301,7 @@
},
{
"BriefDescription": "BL Ring in Use; Any",
+ "Counter": "2,3",
"EventCode": "0x1e",
"EventName": "UNC_C_RING_IV_USED.ANY",
"PerPkg": "1",
@@ -278,6 +310,7 @@
"Unit": "CBOX"
},
{
+ "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.AD_CACHE",
"PerPkg": "1",
@@ -285,6 +318,7 @@
"Unit": "CBOX"
},
{
+ "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.AK_CORE",
"PerPkg": "1",
@@ -292,6 +326,7 @@
"Unit": "CBOX"
},
{
+ "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.BL_CORE",
"PerPkg": "1",
@@ -299,6 +334,7 @@
"Unit": "CBOX"
},
{
+ "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.IV_CORE",
"PerPkg": "1",
@@ -306,6 +342,7 @@
"Unit": "CBOX"
},
{
+ "Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_C_RING_SRC_THRTL",
"PerPkg": "1",
@@ -313,6 +350,7 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
"PerPkg": "1",
@@ -322,6 +360,7 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
"PerPkg": "1",
@@ -331,6 +370,7 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.ISMQ",
"PerPkg": "1",
@@ -340,6 +380,7 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
"PerPkg": "1",
@@ -349,6 +390,7 @@
},
{
"BriefDescription": "Ingress Allocations; IPQ",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IPQ",
"PerPkg": "1",
@@ -358,6 +400,7 @@
},
{
"BriefDescription": "Ingress Allocations; IRQ",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ",
"PerPkg": "1",
@@ -367,6 +410,7 @@
},
{
"BriefDescription": "Ingress Allocations; IRQ Rejected",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED",
"PerPkg": "1",
@@ -376,6 +420,7 @@
},
{
"BriefDescription": "Ingress Allocations; VFIFO",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.VFIFO",
"PerPkg": "1",
@@ -385,6 +430,7 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.IPQ",
"PerPkg": "1",
@@ -394,6 +440,7 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.IRQ",
"PerPkg": "1",
@@ -403,6 +450,7 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
"PerPkg": "1",
@@ -412,6 +460,7 @@
},
{
"BriefDescription": "Probe Queue Retries; Address Conflict",
+ "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
@@ -421,6 +470,7 @@
},
{
"BriefDescription": "Probe Queue Retries; Any Reject",
+ "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
"PerPkg": "1",
@@ -430,6 +480,7 @@
},
{
"BriefDescription": "Probe Queue Retries; No Egress Credits",
+ "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
"PerPkg": "1",
@@ -439,6 +490,7 @@
},
{
"BriefDescription": "Probe Queue Retries; No QPI Credits",
+ "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -448,6 +500,7 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
+ "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
@@ -456,6 +509,7 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; Any Reject",
+ "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
"PerPkg": "1",
@@ -464,6 +518,7 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
+ "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
"PerPkg": "1",
@@ -472,6 +527,7 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
+ "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -480,6 +536,7 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
+ "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
"PerPkg": "1",
@@ -488,6 +545,7 @@
},
{
"BriefDescription": "ISMQ Retries; Any Reject",
+ "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
"PerPkg": "1",
@@ -497,6 +555,7 @@
},
{
"BriefDescription": "ISMQ Retries; No Egress Credits",
+ "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
"PerPkg": "1",
@@ -506,6 +565,7 @@
},
{
"BriefDescription": "ISMQ Retries; No IIO Credits",
+ "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
@@ -515,6 +575,7 @@
},
{
"BriefDescription": "ISMQ Retries; No QPI Credits",
+ "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -524,6 +585,7 @@
},
{
"BriefDescription": "ISMQ Retries; No RTIDs",
+ "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
"PerPkg": "1",
@@ -533,6 +595,7 @@
},
{
"BriefDescription": "Ingress Occupancy; IPQ",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
"PerPkg": "1",
@@ -542,6 +605,7 @@
},
{
"BriefDescription": "Ingress Occupancy; IRQ",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
"PerPkg": "1",
@@ -551,6 +615,7 @@
},
{
"BriefDescription": "Ingress Occupancy; IRQ Rejected",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJECTED",
"PerPkg": "1",
@@ -560,6 +625,7 @@
},
{
"BriefDescription": "Ingress Occupancy; VFIFO",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.VFIFO",
"PerPkg": "1",
@@ -569,6 +635,7 @@
},
{
"BriefDescription": "TOR Inserts; Evictions",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.EVICTION",
"PerPkg": "1",
@@ -578,6 +645,7 @@
},
{
"BriefDescription": "TOR Inserts; Miss All",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_ALL",
"PerPkg": "1",
@@ -587,6 +655,7 @@
},
{
"BriefDescription": "TOR Inserts; Miss Opcode Match",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
"PerPkg": "1",
@@ -596,6 +665,7 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_ALL",
"PerPkg": "1",
@@ -605,6 +675,7 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Evictions",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
"PerPkg": "1",
@@ -614,6 +685,7 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Miss All",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
"PerPkg": "1",
@@ -623,6 +695,7 @@
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
"PerPkg": "1",
@@ -632,6 +705,7 @@
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
"PerPkg": "1",
@@ -641,6 +715,7 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Writebacks",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_WB",
"PerPkg": "1",
@@ -650,6 +725,7 @@
},
{
"BriefDescription": "TOR Inserts; Opcode Match",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.OPCODE",
"PerPkg": "1",
@@ -659,6 +735,7 @@
},
{
"BriefDescription": "TOR Inserts; Writebacks",
+ "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.WB",
"PerPkg": "1",
@@ -668,6 +745,7 @@
},
{
"BriefDescription": "TOR Occupancy; Any",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.ALL",
"PerPkg": "1",
@@ -677,6 +755,7 @@
},
{
"BriefDescription": "TOR Occupancy; Evictions",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
"PerPkg": "1",
@@ -686,6 +765,7 @@
},
{
"BriefDescription": "TOR Occupancy; Miss All",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
"PerPkg": "1",
@@ -695,6 +775,7 @@
},
{
"BriefDescription": "TOR Occupancy; Miss Opcode Match",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
"PerPkg": "1",
@@ -704,6 +785,7 @@
},
{
"BriefDescription": "TOR Occupancy; NID Matched",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
"PerPkg": "1",
@@ -713,6 +795,7 @@
},
{
"BriefDescription": "TOR Occupancy; NID Matched Evictions",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
"PerPkg": "1",
@@ -722,6 +805,7 @@
},
{
"BriefDescription": "TOR Occupancy; NID Matched",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
"PerPkg": "1",
@@ -731,6 +815,7 @@
},
{
"BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
"PerPkg": "1",
@@ -740,6 +825,7 @@
},
{
"BriefDescription": "TOR Occupancy; NID and Opcode Matched",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
"PerPkg": "1",
@@ -749,6 +835,7 @@
},
{
"BriefDescription": "TOR Occupancy; Opcode Match",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
"PerPkg": "1",
@@ -757,6 +844,7 @@
"Unit": "CBOX"
},
{
+ "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED",
"PerPkg": "1",
@@ -764,6 +852,7 @@
},
{
"BriefDescription": "Egress Allocations; AD - Cachebo",
+ "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
"PerPkg": "1",
@@ -773,6 +862,7 @@
},
{
"BriefDescription": "Egress Allocations; AD - Corebo",
+ "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CORE",
"PerPkg": "1",
@@ -782,6 +872,7 @@
},
{
"BriefDescription": "Egress Allocations; AK - Cachebo",
+ "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
"PerPkg": "1",
@@ -791,6 +882,7 @@
},
{
"BriefDescription": "Egress Allocations; AK - Corebo",
+ "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CORE",
"PerPkg": "1",
@@ -800,6 +892,7 @@
},
{
"BriefDescription": "Egress Allocations; BL - Cacheno",
+ "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
"PerPkg": "1",
@@ -809,6 +902,7 @@
},
{
"BriefDescription": "Egress Allocations; BL - Corebo",
+ "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.BL_CORE",
"PerPkg": "1",
@@ -818,6 +912,7 @@
},
{
"BriefDescription": "Egress Allocations; IV - Cachebo",
+ "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
"PerPkg": "1",
@@ -827,6 +922,7 @@
},
{
"BriefDescription": "Injection Starvation; Onto AK Ring",
+ "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AK",
"PerPkg": "1",
@@ -836,6 +932,7 @@
},
{
"BriefDescription": "Injection Starvation; Onto BL Ring",
+ "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.BL",
"PerPkg": "1",
@@ -845,6 +942,7 @@
},
{
"BriefDescription": "HA to iMC Bypass; Not Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
"PerPkg": "1",
@@ -854,6 +952,7 @@
},
{
"BriefDescription": "HA to iMC Bypass; Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_BYPASS_IMC.TAKEN",
"PerPkg": "1",
@@ -863,6 +962,7 @@
},
{
"BriefDescription": "uclks",
+ "Counter": "0,1,2,3",
"EventName": "UNC_H_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
@@ -870,6 +970,7 @@
},
{
"BriefDescription": "Conflict Checks; Conflict Detected",
+ "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT",
"PerPkg": "1",
@@ -878,6 +979,7 @@
},
{
"BriefDescription": "Conflict Checks; No Conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_H_CONFLICT_CYCLES.NO_CONFLICT",
"PerPkg": "1",
@@ -886,6 +988,7 @@
},
{
"BriefDescription": "Direct2Core Messages Sent",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_H_DIRECT2CORE_COUNT",
"PerPkg": "1",
@@ -894,6 +997,7 @@
},
{
"BriefDescription": "Cycles when Direct2Core was Disabled",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
"PerPkg": "1",
@@ -902,6 +1006,7 @@
},
{
"BriefDescription": "Number of Reads that had Direct2Core Overridden",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
@@ -910,6 +1015,7 @@
},
{
"BriefDescription": "Directory Lookups; Snoop Not Needed",
+ "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
"PerPkg": "1",
@@ -919,6 +1025,7 @@
},
{
"BriefDescription": "Directory Lookups; Snoop Needed",
+ "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
"PerPkg": "1",
@@ -928,6 +1035,7 @@
},
{
"BriefDescription": "Directory Updates; Any Directory Update",
+ "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
@@ -937,6 +1045,7 @@
},
{
"BriefDescription": "Directory Updates; Directory Clear",
+ "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
"PerPkg": "1",
@@ -946,6 +1055,7 @@
},
{
"BriefDescription": "Directory Updates; Directory Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.SET",
"PerPkg": "1",
@@ -955,6 +1065,7 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
"PerPkg": "1",
@@ -964,6 +1075,7 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
"PerPkg": "1",
@@ -973,6 +1085,7 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
"PerPkg": "1",
@@ -982,6 +1095,7 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
"PerPkg": "1",
@@ -991,6 +1105,7 @@
},
{
"BriefDescription": "Retry Events",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_H_IMC_RETRY",
"PerPkg": "1",
@@ -998,6 +1113,7 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.ALL",
"PerPkg": "1",
@@ -1007,6 +1123,7 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.FULL",
"PerPkg": "1",
@@ -1016,6 +1133,7 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
@@ -1025,6 +1143,7 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.PARTIAL",
"PerPkg": "1",
@@ -1034,6 +1153,7 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
@@ -1043,6 +1163,7 @@
},
{
"BriefDescription": "Read and Write Requests; Reads",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
@@ -1052,6 +1173,7 @@
},
{
"BriefDescription": "Read and Write Requests; Writes",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES",
"PerPkg": "1",
@@ -1061,6 +1183,7 @@
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
@@ -1070,6 +1193,7 @@
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
@@ -1079,6 +1203,7 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
@@ -1088,6 +1213,7 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CW_ODD",
"PerPkg": "1",
@@ -1097,6 +1223,7 @@
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
@@ -1106,6 +1233,7 @@
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
@@ -1115,6 +1243,7 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
@@ -1124,6 +1253,7 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CW_ODD",
"PerPkg": "1",
@@ -1133,6 +1263,7 @@
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
@@ -1142,6 +1273,7 @@
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
@@ -1151,6 +1283,7 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
@@ -1160,6 +1293,7 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_ODD",
"PerPkg": "1",
@@ -1169,6 +1303,7 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
@@ -1178,6 +1313,7 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
@@ -1187,6 +1323,7 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
@@ -1196,6 +1333,7 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
@@ -1205,6 +1343,7 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
@@ -1214,6 +1353,7 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
@@ -1223,6 +1363,7 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
@@ -1232,6 +1373,7 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
@@ -1241,6 +1383,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
"PerPkg": "1",
@@ -1250,6 +1393,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
"PerPkg": "1",
@@ -1259,6 +1403,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
"PerPkg": "1",
@@ -1268,6 +1413,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
"PerPkg": "1",
@@ -1277,6 +1423,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
"PerPkg": "1",
@@ -1286,6 +1433,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
"PerPkg": "1",
@@ -1295,6 +1443,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
"PerPkg": "1",
@@ -1304,6 +1453,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
"PerPkg": "1",
@@ -1313,6 +1463,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
"PerPkg": "1",
@@ -1322,6 +1473,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
+ "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
"PerPkg": "1",
@@ -1331,6 +1483,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
"PerPkg": "1",
@@ -1340,6 +1493,7 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
"PerPkg": "1",
@@ -1349,6 +1503,7 @@
},
{
"BriefDescription": "Tracker Allocations; All Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_H_TRACKER_INSERTS.ALL",
"PerPkg": "1",
@@ -1358,6 +1513,7 @@
},
{
"BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
+ "Counter": "0,1,2,3",
"EventCode": "0xf",
"EventName": "UNC_H_TxR_AD.NDR",
"PerPkg": "1",
@@ -1367,6 +1523,7 @@
},
{
"BriefDescription": "Outbound NDR Ring Transactions; Snoops",
+ "Counter": "0,1,2,3",
"EventCode": "0xf",
"EventName": "UNC_H_TxR_AD.SNP",
"PerPkg": "1",
@@ -1376,6 +1533,7 @@
},
{
"BriefDescription": "AD Egress Full; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
"PerPkg": "1",
@@ -1384,6 +1542,7 @@
},
{
"BriefDescription": "AD Egress Full; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
"PerPkg": "1",
@@ -1392,6 +1551,7 @@
},
{
"BriefDescription": "AD Egress Full; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
"PerPkg": "1",
@@ -1400,6 +1560,7 @@
},
{
"BriefDescription": "AD Egress Not Empty; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -1408,6 +1569,7 @@
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
"PerPkg": "1",
@@ -1416,6 +1578,7 @@
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
"PerPkg": "1",
@@ -1424,6 +1587,7 @@
},
{
"BriefDescription": "AD Egress Allocations; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.ALL",
"PerPkg": "1",
@@ -1432,6 +1596,7 @@
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
"PerPkg": "1",
@@ -1440,6 +1605,7 @@
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
"PerPkg": "1",
@@ -1448,6 +1614,7 @@
},
{
"BriefDescription": "AD Egress Occupancy; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_H_TxR_AD_OCCUPANCY.ALL",
"PerPkg": "1",
@@ -1456,6 +1623,7 @@
},
{
"BriefDescription": "AD Egress Occupancy; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0",
"PerPkg": "1",
@@ -1464,6 +1632,7 @@
},
{
"BriefDescription": "AD Egress Occupancy; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1",
"PerPkg": "1",
@@ -1472,6 +1641,7 @@
},
{
"BriefDescription": "AK Egress Full; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
@@ -1480,6 +1650,7 @@
},
{
"BriefDescription": "AK Egress Full; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
"PerPkg": "1",
@@ -1488,6 +1659,7 @@
},
{
"BriefDescription": "AK Egress Full; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
"PerPkg": "1",
@@ -1496,6 +1668,7 @@
},
{
"BriefDescription": "AK Egress Not Empty; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -1504,6 +1677,7 @@
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
"PerPkg": "1",
@@ -1512,6 +1686,7 @@
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
"PerPkg": "1",
@@ -1520,6 +1695,7 @@
},
{
"BriefDescription": "AK Egress Allocations; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_H_TxR_AK_INSERTS.ALL",
"PerPkg": "1",
@@ -1528,6 +1704,7 @@
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
"PerPkg": "1",
@@ -1536,6 +1713,7 @@
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
"PerPkg": "1",
@@ -1544,6 +1722,7 @@
},
{
"BriefDescription": "Outbound NDR Ring Transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xe",
"EventName": "UNC_H_TxR_AK_NDR",
"PerPkg": "1",
@@ -1552,6 +1731,7 @@
},
{
"BriefDescription": "AK Egress Occupancy; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_H_TxR_AK_OCCUPANCY.ALL",
"PerPkg": "1",
@@ -1560,6 +1740,7 @@
},
{
"BriefDescription": "AK Egress Occupancy; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0",
"PerPkg": "1",
@@ -1568,6 +1749,7 @@
},
{
"BriefDescription": "AK Egress Occupancy; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1",
"PerPkg": "1",
@@ -1576,6 +1758,7 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CACHE",
"PerPkg": "1",
@@ -1585,6 +1768,7 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CORE",
"PerPkg": "1",
@@ -1594,6 +1778,7 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_QPI",
"PerPkg": "1",
@@ -1603,6 +1788,7 @@
},
{
"BriefDescription": "BL Egress Full; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
"PerPkg": "1",
@@ -1611,6 +1797,7 @@
},
{
"BriefDescription": "BL Egress Full; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
"PerPkg": "1",
@@ -1619,6 +1806,7 @@
},
{
"BriefDescription": "BL Egress Full; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
"PerPkg": "1",
@@ -1627,6 +1815,7 @@
},
{
"BriefDescription": "BL Egress Not Empty; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -1635,6 +1824,7 @@
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
"PerPkg": "1",
@@ -1643,6 +1833,7 @@
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
"PerPkg": "1",
@@ -1651,6 +1842,7 @@
},
{
"BriefDescription": "BL Egress Allocations; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.ALL",
"PerPkg": "1",
@@ -1659,6 +1851,7 @@
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
"PerPkg": "1",
@@ -1667,6 +1860,7 @@
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
"PerPkg": "1",
@@ -1675,6 +1869,7 @@
},
{
"BriefDescription": "BL Egress Occupancy; All",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL",
"PerPkg": "1",
@@ -1683,6 +1878,7 @@
},
{
"BriefDescription": "BL Egress Occupancy; Scheduler 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0",
"PerPkg": "1",
@@ -1691,6 +1887,7 @@
},
{
"BriefDescription": "BL Egress Occupancy; Scheduler 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1",
"PerPkg": "1",
@@ -1699,6 +1896,7 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
@@ -1708,6 +1906,7 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
@@ -1717,6 +1916,7 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
@@ -1726,6 +1926,7 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
@@ -1735,6 +1936,7 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
@@ -1744,6 +1946,7 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
@@ -1753,6 +1956,7 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
@@ -1762,6 +1966,7 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json
index 0fc907e5cf3c..36b1946f06f2 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Address Match (Conflict) Count; Conflict Merges",
+ "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT",
"PerPkg": "1",
@@ -10,6 +11,7 @@
},
{
"BriefDescription": "Address Match (Conflict) Count; Conflict Stalls",
+ "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT",
"PerPkg": "1",
@@ -19,6 +21,7 @@
},
{
"BriefDescription": "Write Ack Pending Occupancy; Any Source",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -28,6 +31,7 @@
},
{
"BriefDescription": "Write Ack Pending Occupancy; Select Source",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -37,6 +41,7 @@
},
{
"BriefDescription": "Outstanding Write Ownership Occupancy; Any Source",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -46,6 +51,7 @@
},
{
"BriefDescription": "Outstanding Write Ownership Occupancy; Select Source",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -55,6 +61,7 @@
},
{
"BriefDescription": "Outstanding Read Occupancy; Any Source",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -64,6 +71,7 @@
},
{
"BriefDescription": "Outstanding Read Occupancy; Select Source",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -73,6 +81,7 @@
},
{
"BriefDescription": "Total Write Cache Occupancy; Any Source",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -82,6 +91,7 @@
},
{
"BriefDescription": "Total Write Cache Occupancy; Select Source",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -91,6 +101,7 @@
},
{
"BriefDescription": "Outstanding Write Occupancy; Any Source",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -100,6 +111,7 @@
},
{
"BriefDescription": "Outstanding Write Occupancy; Select Source",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -109,12 +121,14 @@
},
{
"BriefDescription": "Clocks in the IRP",
+ "Counter": "0,1",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Number of clocks in the IRP.",
"Unit": "IRP"
},
{
+ "Counter": "0,1",
"EventCode": "0xB",
"EventName": "UNC_I_RxR_AK_CYCLES_FULL",
"PerPkg": "1",
@@ -123,6 +137,7 @@
},
{
"BriefDescription": "AK Ingress Occupancy",
+ "Counter": "0,1",
"EventCode": "0xA",
"EventName": "UNC_I_RxR_AK_INSERTS",
"PerPkg": "1",
@@ -130,6 +145,7 @@
"Unit": "IRP"
},
{
+ "Counter": "0,1",
"EventCode": "0xC",
"EventName": "UNC_I_RxR_AK_OCCUPANCY",
"PerPkg": "1",
@@ -137,6 +153,7 @@
"Unit": "IRP"
},
{
+ "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
@@ -145,6 +162,7 @@
},
{
"BriefDescription": "BL Ingress Occupancy - DRS",
+ "Counter": "0,1",
"EventCode": "0x1",
"EventName": "UNC_I_RxR_BL_DRS_INSERTS",
"PerPkg": "1",
@@ -152,6 +170,7 @@
"Unit": "IRP"
},
{
+ "Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
@@ -159,6 +178,7 @@
"Unit": "IRP"
},
{
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
@@ -167,6 +187,7 @@
},
{
"BriefDescription": "BL Ingress Occupancy - NCB",
+ "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_I_RxR_BL_NCB_INSERTS",
"PerPkg": "1",
@@ -174,6 +195,7 @@
"Unit": "IRP"
},
{
+ "Counter": "0,1",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
@@ -181,6 +203,7 @@
"Unit": "IRP"
},
{
+ "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
@@ -189,6 +212,7 @@
},
{
"BriefDescription": "BL Ingress Occupancy - NCS",
+ "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_I_RxR_BL_NCS_INSERTS",
"PerPkg": "1",
@@ -196,6 +220,7 @@
"Unit": "IRP"
},
{
+ "Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
@@ -204,6 +229,7 @@
},
{
"BriefDescription": "Tickle Count; Ownership Lost",
+ "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TICKLES.LOST_OWNERSHIP",
"PerPkg": "1",
@@ -213,6 +239,7 @@
},
{
"BriefDescription": "Tickle Count; Data Returned",
+ "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TICKLES.TOP_OF_QUEUE",
"PerPkg": "1",
@@ -222,6 +249,7 @@
},
{
"BriefDescription": "Inbound Transaction Count; Read Prefetches",
+ "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES",
"PerPkg": "1",
@@ -231,6 +259,7 @@
},
{
"BriefDescription": "Inbound Transaction Count; Reads",
+ "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
@@ -240,6 +269,7 @@
},
{
"BriefDescription": "Inbound Transaction Count; Writes",
+ "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
@@ -249,6 +279,7 @@
},
{
"BriefDescription": "No AD Egress Credit Stalls",
+ "Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
@@ -257,6 +288,7 @@
},
{
"BriefDescription": "No BL Egress Credit Stalls",
+ "Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
@@ -265,6 +297,7 @@
},
{
"BriefDescription": "Outbound Read Requests",
+ "Counter": "0,1",
"EventCode": "0xE",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
"PerPkg": "1",
@@ -273,6 +306,7 @@
},
{
"BriefDescription": "Outbound Read Requests",
+ "Counter": "0,1",
"EventCode": "0xF",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
"PerPkg": "1",
@@ -281,6 +315,7 @@
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
+ "Counter": "0,1",
"EventCode": "0xD",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
@@ -289,6 +324,7 @@
},
{
"BriefDescription": "Write Ordering Stalls",
+ "Counter": "0,1",
"EventCode": "0x1A",
"EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES",
"PerPkg": "1",
@@ -297,6 +333,7 @@
},
{
"BriefDescription": "Number of qfclks",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_CLOCKTICKS",
"PerPkg": "1",
@@ -305,6 +342,7 @@
},
{
"BriefDescription": "Count of CTO Events",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_Q_CTO_COUNT",
"PerPkg": "1",
@@ -313,6 +351,7 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
"PerPkg": "1",
@@ -322,6 +361,7 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
"PerPkg": "1",
@@ -331,6 +371,7 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Not Set",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT",
"PerPkg": "1",
@@ -340,6 +381,7 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Success",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.SUCCESS",
"PerPkg": "1",
@@ -349,6 +391,7 @@
},
{
"BriefDescription": "Cycles in L1",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_L1_POWER_CYCLES",
"PerPkg": "1",
@@ -357,6 +400,7 @@
},
{
"BriefDescription": "Cycles in L0p",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL0P_POWER_CYCLES",
"PerPkg": "1",
@@ -365,6 +409,7 @@
},
{
"BriefDescription": "Cycles in L0",
+ "Counter": "0,1,2,3",
"EventCode": "0xf",
"EventName": "UNC_Q_RxL0_POWER_CYCLES",
"PerPkg": "1",
@@ -373,6 +418,7 @@
},
{
"BriefDescription": "Rx Flit Buffer Bypassed",
+ "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_BYPASSED",
"PerPkg": "1",
@@ -381,6 +427,7 @@
},
{
"BriefDescription": "CRC Errors Detected; LinkInit",
+ "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
"PerPkg": "1",
@@ -390,6 +437,7 @@
},
{
"BriefDescription": "CRC Errors Detected; Normal Operations",
+ "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
"PerPkg": "1",
@@ -399,6 +447,7 @@
},
{
"BriefDescription": "VN0 Credit Consumed; DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
"PerPkg": "1",
@@ -408,6 +457,7 @@
},
{
"BriefDescription": "VN0 Credit Consumed; HOM",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
"PerPkg": "1",
@@ -417,6 +467,7 @@
},
{
"BriefDescription": "VN0 Credit Consumed; NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
"PerPkg": "1",
@@ -426,6 +477,7 @@
},
{
"BriefDescription": "VN0 Credit Consumed; NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
"PerPkg": "1",
@@ -435,6 +487,7 @@
},
{
"BriefDescription": "VN0 Credit Consumed; NDR",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
"PerPkg": "1",
@@ -444,6 +497,7 @@
},
{
"BriefDescription": "VN0 Credit Consumed; SNP",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
"PerPkg": "1",
@@ -453,6 +507,7 @@
},
{
"BriefDescription": "VNA Credit Consumed",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
"PerPkg": "1",
@@ -461,6 +516,7 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_Q_RxL_CYCLES_NE",
"PerPkg": "1",
@@ -469,6 +525,7 @@
},
{
"BriefDescription": "Flits Received - Group 0; Data Tx Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.DATA",
"PerPkg": "1",
@@ -478,6 +535,7 @@
},
{
"BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
"PerPkg": "1",
@@ -487,6 +545,7 @@
},
{
"BriefDescription": "Flits Received - Group 0; Non-Data protocol Tx Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
@@ -496,6 +555,7 @@
},
{
"BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS",
"PerPkg": "1",
@@ -505,6 +565,7 @@
},
{
"BriefDescription": "Flits Received - Group 1; DRS Data Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
"PerPkg": "1",
@@ -514,6 +575,7 @@
},
{
"BriefDescription": "Flits Received - Group 1; DRS Header Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
"PerPkg": "1",
@@ -523,6 +585,7 @@
},
{
"BriefDescription": "Flits Received - Group 1; HOM Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM",
"PerPkg": "1",
@@ -532,6 +595,7 @@
},
{
"BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
"PerPkg": "1",
@@ -541,6 +605,7 @@
},
{
"BriefDescription": "Flits Received - Group 1; HOM Request Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
"PerPkg": "1",
@@ -550,6 +615,7 @@
},
{
"BriefDescription": "Flits Received - Group 1; SNP Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.SNP",
"PerPkg": "1",
@@ -559,6 +625,7 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB",
"PerPkg": "1",
@@ -568,6 +635,7 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
"PerPkg": "1",
@@ -577,6 +645,7 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
"PerPkg": "1",
@@ -586,6 +655,7 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCS",
"PerPkg": "1",
@@ -595,6 +665,7 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
"PerPkg": "1",
@@ -604,6 +675,7 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
+ "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
"PerPkg": "1",
@@ -613,6 +685,7 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_Q_RxL_INSERTS",
"PerPkg": "1",
@@ -621,6 +694,7 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS",
"PerPkg": "1",
@@ -629,6 +703,7 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM",
+ "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_Q_RxL_INSERTS_HOM",
"PerPkg": "1",
@@ -637,6 +712,7 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_Q_RxL_INSERTS_NCB",
"PerPkg": "1",
@@ -645,6 +721,7 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_Q_RxL_INSERTS_NCS",
"PerPkg": "1",
@@ -653,6 +730,7 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR",
+ "Counter": "0,1,2,3",
"EventCode": "0xe",
"EventName": "UNC_Q_RxL_INSERTS_NDR",
"PerPkg": "1",
@@ -661,6 +739,7 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP",
+ "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_Q_RxL_INSERTS_SNP",
"PerPkg": "1",
@@ -669,6 +748,7 @@
},
{
"BriefDescription": "RxQ Occupancy - All Packets",
+ "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_Q_RxL_OCCUPANCY",
"PerPkg": "1",
@@ -677,6 +757,7 @@
},
{
"BriefDescription": "RxQ Occupancy - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS",
"PerPkg": "1",
@@ -685,6 +766,7 @@
},
{
"BriefDescription": "RxQ Occupancy - HOM",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM",
"PerPkg": "1",
@@ -693,6 +775,7 @@
},
{
"BriefDescription": "RxQ Occupancy - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB",
"PerPkg": "1",
@@ -701,6 +784,7 @@
},
{
"BriefDescription": "RxQ Occupancy - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS",
"PerPkg": "1",
@@ -709,6 +793,7 @@
},
{
"BriefDescription": "RxQ Occupancy - NDR",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR",
"PerPkg": "1",
@@ -717,6 +802,7 @@
},
{
"BriefDescription": "RxQ Occupancy - SNP",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP",
"PerPkg": "1",
@@ -725,6 +811,7 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - HOM",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_DRS",
"PerPkg": "1",
@@ -734,6 +821,7 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_HOM",
"PerPkg": "1",
@@ -743,6 +831,7 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - SNP",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_NCB",
"PerPkg": "1",
@@ -752,6 +841,7 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NDR",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_NCS",
"PerPkg": "1",
@@ -761,6 +851,7 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_NDR",
"PerPkg": "1",
@@ -770,6 +861,7 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_SNP",
"PerPkg": "1",
@@ -779,6 +871,7 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; Egress Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.EGRESS_CREDITS",
"PerPkg": "1",
@@ -788,6 +881,7 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; GV",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.GV",
"PerPkg": "1",
@@ -797,6 +891,7 @@
},
{
"BriefDescription": "Cycles in L0p",
+ "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_Q_TxL0P_POWER_CYCLES",
"PerPkg": "1",
@@ -805,6 +900,7 @@
},
{
"BriefDescription": "Cycles in L0",
+ "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_Q_TxL0_POWER_CYCLES",
"PerPkg": "1",
@@ -813,6 +909,7 @@
},
{
"BriefDescription": "Tx Flit Buffer Bypassed",
+ "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_Q_TxL_BYPASSED",
"PerPkg": "1",
@@ -821,6 +918,7 @@
},
{
"BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
"PerPkg": "1",
@@ -830,6 +928,7 @@
},
{
"BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
"PerPkg": "1",
@@ -839,6 +938,7 @@
},
{
"BriefDescription": "Tx Flit Buffer Cycles not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_Q_TxL_CYCLES_NE",
"PerPkg": "1",
@@ -847,6 +947,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
+ "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.DATA",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
@@ -855,6 +956,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 0; Idle and Null Flits",
+ "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.IDLE",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
@@ -863,6 +965,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
+ "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
@@ -871,6 +974,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
+ "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
@@ -879,6 +983,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
+ "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
@@ -887,6 +992,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
+ "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
@@ -895,6 +1001,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Flits",
+ "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
@@ -903,6 +1010,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
+ "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
@@ -911,6 +1019,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
+ "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
@@ -919,6 +1028,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; SNP Flits",
+ "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.SNP",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
@@ -927,6 +1037,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB",
"PerPkg": "1",
@@ -936,6 +1047,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
"PerPkg": "1",
@@ -945,6 +1057,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
"PerPkg": "1",
@@ -954,6 +1067,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCS",
"PerPkg": "1",
@@ -963,6 +1077,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
"PerPkg": "1",
@@ -972,6 +1087,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
"PerPkg": "1",
@@ -981,6 +1097,7 @@
},
{
"BriefDescription": "Tx Flit Buffer Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_Q_TxL_INSERTS",
"PerPkg": "1",
@@ -989,6 +1106,7 @@
},
{
"BriefDescription": "Tx Flit Buffer Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_Q_TxL_OCCUPANCY",
"PerPkg": "1",
@@ -997,6 +1115,7 @@
},
{
"BriefDescription": "VNA Credits Returned",
+ "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_Q_VNA_CREDIT_RETURNS",
"PerPkg": "1",
@@ -1005,6 +1124,7 @@
},
{
"BriefDescription": "VNA Credits Pending Return - Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
"PerPkg": "1",
@@ -1013,6 +1133,7 @@
},
{
"BriefDescription": "Number of uclks in domain",
+ "Counter": "0,1,2",
"EventCode": "0x1",
"EventName": "UNC_R3_CLOCKTICKS",
"PerPkg": "1",
@@ -1021,6 +1142,7 @@
},
{
"BriefDescription": "to IIO BL Credit Acquired",
+ "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
@@ -1030,6 +1152,7 @@
},
{
"BriefDescription": "to IIO BL Credit Acquired",
+ "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
@@ -1039,6 +1162,7 @@
},
{
"BriefDescription": "to IIO BL Credit Acquired",
+ "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
@@ -1048,6 +1172,7 @@
},
{
"BriefDescription": "to IIO BL Credit Rejected",
+ "Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_IIO_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -1057,6 +1182,7 @@
},
{
"BriefDescription": "to IIO BL Credit Rejected",
+ "Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_IIO_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -1066,6 +1192,7 @@
},
{
"BriefDescription": "to IIO BL Credit Rejected",
+ "Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_IIO_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -1075,6 +1202,7 @@
},
{
"BriefDescription": "to IIO BL Credit In Use",
+ "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
@@ -1084,6 +1212,7 @@
},
{
"BriefDescription": "to IIO BL Credit In Use",
+ "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
@@ -1093,6 +1222,7 @@
},
{
"BriefDescription": "to IIO BL Credit In Use",
+ "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
@@ -1102,6 +1232,7 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
+ "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
@@ -1111,6 +1242,7 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
+ "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
@@ -1120,6 +1252,7 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
+ "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
@@ -1129,6 +1262,7 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
+ "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW_ODD",
"PerPkg": "1",
@@ -1138,6 +1272,7 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
+ "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
@@ -1147,6 +1282,7 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
+ "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
@@ -1156,6 +1292,7 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
+ "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
@@ -1165,6 +1302,7 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
+ "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW_ODD",
"PerPkg": "1",
@@ -1174,6 +1312,7 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
+ "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
@@ -1183,6 +1322,7 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
+ "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
@@ -1192,6 +1332,7 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
+ "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
@@ -1201,6 +1342,7 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
+ "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW_ODD",
"PerPkg": "1",
@@ -1210,6 +1352,7 @@
},
{
"BriefDescription": "R3 IV Ring in Use; Any",
+ "Counter": "0,1,2",
"EventCode": "0xa",
"EventName": "UNC_R3_RING_IV_USED.ANY",
"PerPkg": "1",
@@ -1219,6 +1362,7 @@
},
{
"BriefDescription": "Ingress Bypassed",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_R3_RxR_BYPASSED.AD",
"PerPkg": "1",
@@ -1228,6 +1372,7 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; DRS",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.DRS",
"PerPkg": "1",
@@ -1237,6 +1382,7 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; HOM",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
"PerPkg": "1",
@@ -1246,6 +1392,7 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
@@ -1255,6 +1402,7 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
@@ -1264,6 +1412,7 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NDR",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
"PerPkg": "1",
@@ -1273,6 +1422,7 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; SNP",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
"PerPkg": "1",
@@ -1282,6 +1432,7 @@
},
{
"BriefDescription": "Ingress Allocations; DRS",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.DRS",
"PerPkg": "1",
@@ -1291,6 +1442,7 @@
},
{
"BriefDescription": "Ingress Allocations; HOM",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.HOM",
"PerPkg": "1",
@@ -1300,6 +1452,7 @@
},
{
"BriefDescription": "Ingress Allocations; NCB",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCB",
"PerPkg": "1",
@@ -1309,6 +1462,7 @@
},
{
"BriefDescription": "Ingress Allocations; NCS",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCS",
"PerPkg": "1",
@@ -1318,6 +1472,7 @@
},
{
"BriefDescription": "Ingress Allocations; NDR",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NDR",
"PerPkg": "1",
@@ -1327,6 +1482,7 @@
},
{
"BriefDescription": "Ingress Allocations; SNP",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.SNP",
"PerPkg": "1",
@@ -1336,6 +1492,7 @@
},
{
"BriefDescription": "Ingress Occupancy Accumulator; DRS",
+ "Counter": "0",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY.DRS",
"PerPkg": "1",
@@ -1345,6 +1502,7 @@
},
{
"BriefDescription": "Ingress Occupancy Accumulator; HOM",
+ "Counter": "0",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY.HOM",
"PerPkg": "1",
@@ -1354,6 +1512,7 @@
},
{
"BriefDescription": "Ingress Occupancy Accumulator; NCB",
+ "Counter": "0",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY.NCB",
"PerPkg": "1",
@@ -1363,6 +1522,7 @@
},
{
"BriefDescription": "Ingress Occupancy Accumulator; NCS",
+ "Counter": "0",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY.NCS",
"PerPkg": "1",
@@ -1372,6 +1532,7 @@
},
{
"BriefDescription": "Ingress Occupancy Accumulator; NDR",
+ "Counter": "0",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY.NDR",
"PerPkg": "1",
@@ -1381,6 +1542,7 @@
},
{
"BriefDescription": "Ingress Occupancy Accumulator; SNP",
+ "Counter": "0",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY.SNP",
"PerPkg": "1",
@@ -1390,6 +1552,7 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -1399,6 +1562,7 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
"PerPkg": "1",
@@ -1408,6 +1572,7 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -1417,6 +1582,7 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -1426,6 +1592,7 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
"PerPkg": "1",
@@ -1435,6 +1602,7 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
+ "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
"PerPkg": "1",
@@ -1444,6 +1612,7 @@
},
{
"BriefDescription": "VN0 Credit Used; DRS Message Class",
+ "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
"PerPkg": "1",
@@ -1453,6 +1622,7 @@
},
{
"BriefDescription": "VN0 Credit Used; HOM Message Class",
+ "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
"PerPkg": "1",
@@ -1462,6 +1632,7 @@
},
{
"BriefDescription": "VN0 Credit Used; NCB Message Class",
+ "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
@@ -1471,6 +1642,7 @@
},
{
"BriefDescription": "VN0 Credit Used; NCS Message Class",
+ "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
@@ -1480,6 +1652,7 @@
},
{
"BriefDescription": "VN0 Credit Used; NDR Message Class",
+ "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
"PerPkg": "1",
@@ -1489,6 +1662,7 @@
},
{
"BriefDescription": "VN0 Credit Used; SNP Message Class",
+ "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
@@ -1498,6 +1672,7 @@
},
{
"BriefDescription": "VNA credit Acquisitions",
+ "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED",
"PerPkg": "1",
@@ -1506,6 +1681,7 @@
},
{
"BriefDescription": "VNA Credit Reject; DRS Message Class",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -1515,6 +1691,7 @@
},
{
"BriefDescription": "VNA Credit Reject; HOM Message Class",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
"PerPkg": "1",
@@ -1524,6 +1701,7 @@
},
{
"BriefDescription": "VNA Credit Reject; NCB Message Class",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -1533,6 +1711,7 @@
},
{
"BriefDescription": "VNA Credit Reject; NCS Message Class",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -1542,6 +1721,7 @@
},
{
"BriefDescription": "VNA Credit Reject; NDR Message Class",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
"PerPkg": "1",
@@ -1551,6 +1731,7 @@
},
{
"BriefDescription": "VNA Credit Reject; SNP Message Class",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
"PerPkg": "1",
@@ -1560,6 +1741,7 @@
},
{
"BriefDescription": "Cycles with no VNA credits available",
+ "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT",
"PerPkg": "1",
@@ -1568,6 +1750,7 @@
},
{
"BriefDescription": "Cycles with 1 or more VNA credits in use",
+ "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED",
"PerPkg": "1",
@@ -1575,12 +1758,14 @@
"Unit": "R3QPI"
},
{
+ "Counter": "0,1",
"EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "UBOX"
},
{
"BriefDescription": "VLW Received",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
@@ -1590,6 +1775,7 @@
},
{
"BriefDescription": "VLW Received",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.INT_PRIO",
"PerPkg": "1",
@@ -1599,6 +1785,7 @@
},
{
"BriefDescription": "VLW Received",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
"PerPkg": "1",
@@ -1608,6 +1795,7 @@
},
{
"BriefDescription": "VLW Received",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
"PerPkg": "1",
@@ -1617,6 +1805,7 @@
},
{
"BriefDescription": "VLW Received",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
"PerPkg": "1",
@@ -1626,6 +1815,7 @@
},
{
"BriefDescription": "Filter Match",
+ "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.DISABLE",
"PerPkg": "1",
@@ -1635,6 +1825,7 @@
},
{
"BriefDescription": "Filter Match",
+ "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.ENABLE",
"PerPkg": "1",
@@ -1644,6 +1835,7 @@
},
{
"BriefDescription": "Filter Match",
+ "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
"PerPkg": "1",
@@ -1653,6 +1845,7 @@
},
{
"BriefDescription": "Filter Match",
+ "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
"PerPkg": "1",
@@ -1662,6 +1855,7 @@
},
{
"BriefDescription": "IDI Lock/SplitLock Cycles",
+ "Counter": "0,1",
"EventCode": "0x44",
"EventName": "UNC_U_LOCK_CYCLES",
"PerPkg": "1",
@@ -1670,6 +1864,7 @@
},
{
"BriefDescription": "MsgCh Requests by Size; 4B Requests",
+ "Counter": "0,1",
"EventCode": "0x47",
"EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.4B",
"PerPkg": "1",
@@ -1679,6 +1874,7 @@
},
{
"BriefDescription": "MsgCh Requests by Size; 8B Requests",
+ "Counter": "0,1",
"EventCode": "0x47",
"EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.8B",
"PerPkg": "1",
@@ -1688,6 +1884,7 @@
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; ACK to Deassert",
+ "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT",
"PerPkg": "1",
@@ -1697,6 +1894,7 @@
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+ "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
@@ -1706,6 +1904,7 @@
},
{
"BriefDescription": "RACU Request",
+ "Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS.COUNT",
"PerPkg": "1",
@@ -1714,6 +1913,7 @@
},
{
"BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.CMC",
"PerPkg": "1",
@@ -1723,6 +1923,7 @@
},
{
"BriefDescription": "Monitor Sent to T0; Livelock",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
"PerPkg": "1",
@@ -1732,6 +1933,7 @@
},
{
"BriefDescription": "Monitor Sent to T0; LTError",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LTERROR",
"PerPkg": "1",
@@ -1741,6 +1943,7 @@
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T0",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
"PerPkg": "1",
@@ -1750,6 +1953,7 @@
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T1",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
"PerPkg": "1",
@@ -1759,6 +1963,7 @@
},
{
"BriefDescription": "Monitor Sent to T0; Other",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.OTHER",
"PerPkg": "1",
@@ -1768,6 +1973,7 @@
},
{
"BriefDescription": "Monitor Sent to T0; Trap",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.TRAP",
"PerPkg": "1",
@@ -1777,6 +1983,7 @@
},
{
"BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.UMC",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json
index b1ce5f77675e..c49f11aca14e 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Number of uclks in domain",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_R2_CLOCKTICKS",
"PerPkg": "1",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
+ "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
@@ -18,6 +20,7 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
+ "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
@@ -27,6 +30,7 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
+ "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
@@ -36,6 +40,7 @@
},
{
"BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -45,6 +50,7 @@
},
{
"BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCB",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R2_IIO_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -54,6 +60,7 @@
},
{
"BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCS",
+ "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R2_IIO_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -63,6 +70,7 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; DRS",
+ "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
@@ -72,6 +80,7 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCB",
+ "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
@@ -81,6 +90,7 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCS",
+ "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
@@ -90,6 +100,7 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
@@ -99,6 +110,7 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
@@ -108,6 +120,7 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
@@ -117,6 +130,7 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_ODD",
"PerPkg": "1",
@@ -126,6 +140,7 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
@@ -135,6 +150,7 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
@@ -144,6 +160,7 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
@@ -153,6 +170,7 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_ODD",
"PerPkg": "1",
@@ -162,6 +180,7 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
@@ -171,6 +190,7 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
@@ -180,6 +200,7 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
@@ -189,6 +210,7 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_ODD",
"PerPkg": "1",
@@ -198,6 +220,7 @@
},
{
"BriefDescription": "R2 IV Ring in Use; Any",
+ "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_R2_RING_IV_USED.ANY",
"PerPkg": "1",
@@ -207,6 +230,7 @@
},
{
"BriefDescription": "AK Ingress Bounced",
+ "Counter": "0",
"EventCode": "0x12",
"EventName": "UNC_R2_RxR_AK_BOUNCES",
"PerPkg": "1",
@@ -215,6 +239,7 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; DRS",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.DRS",
"PerPkg": "1",
@@ -224,6 +249,7 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
@@ -233,6 +259,7 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
@@ -242,6 +269,7 @@
},
{
"BriefDescription": "Egress Cycles Full; AD",
+ "Counter": "0",
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
"PerPkg": "1",
@@ -251,6 +279,7 @@
},
{
"BriefDescription": "Egress Cycles Full; AK",
+ "Counter": "0",
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
"PerPkg": "1",
@@ -260,6 +289,7 @@
},
{
"BriefDescription": "Egress Cycles Full; BL",
+ "Counter": "0",
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
"PerPkg": "1",
@@ -269,6 +299,7 @@
},
{
"BriefDescription": "Egress Cycles Not Empty; AD",
+ "Counter": "0",
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.AD",
"PerPkg": "1",
@@ -278,6 +309,7 @@
},
{
"BriefDescription": "Egress Cycles Not Empty; AK",
+ "Counter": "0",
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.AK",
"PerPkg": "1",
@@ -287,6 +319,7 @@
},
{
"BriefDescription": "Egress Cycles Not Empty; BL",
+ "Counter": "0",
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.BL",
"PerPkg": "1",
@@ -296,6 +329,7 @@
},
{
"BriefDescription": "Egress NACK; AD",
+ "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACKS.AD",
"PerPkg": "1",
@@ -305,6 +339,7 @@
},
{
"BriefDescription": "Egress NACK; AK",
+ "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACKS.AK",
"PerPkg": "1",
@@ -314,6 +349,7 @@
},
{
"BriefDescription": "Egress NACK; BL",
+ "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACKS.BL",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json
index 6dcc9415a462..c94e22cdb535 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "DRAM Activate Count",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT",
"PerPkg": "1",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
@@ -25,6 +28,7 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
@@ -33,6 +37,7 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
@@ -41,6 +46,7 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
@@ -49,6 +55,7 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
@@ -57,6 +64,7 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
@@ -65,6 +73,7 @@
},
{
"BriefDescription": "uclks",
+ "Counter": "0,1,2,3",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Uncore Fixed Counter - uclks",
@@ -72,6 +81,7 @@
},
{
"BriefDescription": "DRAM Precharge All Commands",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
@@ -80,6 +90,7 @@
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
@@ -89,6 +100,7 @@
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
@@ -98,6 +110,7 @@
},
{
"BriefDescription": "ECC Correctable Errors",
+ "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
@@ -106,6 +119,7 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
@@ -115,6 +129,7 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
@@ -124,6 +139,7 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Read Major Mode",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.READ",
"PerPkg": "1",
@@ -133,6 +149,7 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Write Major Mode",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
@@ -142,6 +159,7 @@
},
{
"BriefDescription": "Channel DLLOFF Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
@@ -150,6 +168,7 @@
},
{
"BriefDescription": "Channel PPD Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
@@ -158,6 +177,7 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
@@ -167,6 +187,7 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
@@ -176,6 +197,7 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
@@ -185,6 +207,7 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
@@ -194,6 +217,7 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
@@ -203,6 +227,7 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
@@ -212,6 +237,7 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
@@ -221,6 +247,7 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
@@ -230,6 +257,7 @@
},
{
"BriefDescription": "Critical Throttle Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"PerPkg": "1",
@@ -238,6 +266,7 @@
},
{
"BriefDescription": "Clock-Enabled Self-Refresh",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
@@ -246,6 +275,7 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
@@ -255,6 +285,7 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
@@ -264,6 +295,7 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
@@ -273,6 +305,7 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
@@ -282,6 +315,7 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
@@ -291,6 +325,7 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
@@ -300,6 +335,7 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
@@ -309,6 +345,7 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
@@ -318,6 +355,7 @@
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
@@ -327,6 +365,7 @@
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
@@ -336,6 +375,7 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
@@ -345,6 +385,7 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
"PerPkg": "1",
@@ -354,6 +395,7 @@
},
{
"BriefDescription": "Read Pending Queue Full Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M_RPQ_CYCLES_FULL",
"PerPkg": "1",
@@ -362,6 +404,7 @@
},
{
"BriefDescription": "Read Pending Queue Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
@@ -370,6 +413,7 @@
},
{
"BriefDescription": "Read Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS",
"PerPkg": "1",
@@ -378,6 +422,7 @@
},
{
"BriefDescription": "Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M_RPQ_OCCUPANCY",
"PerPkg": "1",
@@ -386,6 +431,7 @@
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
@@ -394,6 +440,7 @@
},
{
"BriefDescription": "Write Pending Queue Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
@@ -402,6 +449,7 @@
},
{
"BriefDescription": "Write Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M_WPQ_INSERTS",
"PerPkg": "1",
@@ -410,6 +458,7 @@
},
{
"BriefDescription": "Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M_WPQ_OCCUPANCY",
"PerPkg": "1",
@@ -418,6 +467,7 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
@@ -426,6 +476,7 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json
index 6f98fc1728e6..1dffd2999d70 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "pclk Cycles",
+ "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -16,6 +18,7 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -24,6 +27,7 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -32,6 +36,7 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -40,6 +45,7 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -48,6 +54,7 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -56,6 +63,7 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -64,6 +72,7 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -72,6 +81,7 @@
},
{
"BriefDescription": "Core C State Demotions",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
@@ -80,6 +90,7 @@
},
{
"BriefDescription": "Core C State Demotions",
+ "Counter": "0,1,2,3",
"EventCode": "0x1f",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
@@ -88,6 +99,7 @@
},
{
"BriefDescription": "Core C State Demotions",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
@@ -96,6 +108,7 @@
},
{
"BriefDescription": "Core C State Demotions",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
@@ -104,6 +117,7 @@
},
{
"BriefDescription": "Core C State Demotions",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
@@ -112,6 +126,7 @@
},
{
"BriefDescription": "Core C State Demotions",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
@@ -120,6 +135,7 @@
},
{
"BriefDescription": "Core C State Demotions",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
@@ -128,6 +144,7 @@
},
{
"BriefDescription": "Core C State Demotions",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
@@ -136,6 +153,7 @@
},
{
"BriefDescription": "Frequency Residency",
+ "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_P_FREQ_BAND0_CYCLES",
"PerPkg": "1",
@@ -144,6 +162,7 @@
},
{
"BriefDescription": "Frequency Residency",
+ "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_P_FREQ_BAND1_CYCLES",
"PerPkg": "1",
@@ -152,6 +171,7 @@
},
{
"BriefDescription": "Frequency Residency",
+ "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_P_FREQ_BAND2_CYCLES",
"PerPkg": "1",
@@ -160,6 +180,7 @@
},
{
"BriefDescription": "Frequency Residency",
+ "Counter": "0,1,2,3",
"EventCode": "0xe",
"EventName": "UNC_P_FREQ_BAND3_CYCLES",
"PerPkg": "1",
@@ -168,6 +189,7 @@
},
{
"BriefDescription": "Current Strongest Upper Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES",
"PerPkg": "1",
@@ -176,6 +198,7 @@
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
@@ -184,6 +207,7 @@
},
{
"BriefDescription": "OS Strongest Upper Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"PerPkg": "1",
@@ -192,6 +216,7 @@
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
@@ -200,6 +225,7 @@
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
@@ -208,6 +234,7 @@
},
{
"BriefDescription": "Perf P Limit Strongest Lower Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES",
"PerPkg": "1",
@@ -216,6 +243,7 @@
},
{
"BriefDescription": "Cycles spent changing Frequency",
+ "Counter": "0,1,2,3",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
@@ -223,6 +251,7 @@
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
@@ -231,6 +260,7 @@
},
{
"BriefDescription": "Number of cores in C0",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"Filter": "occ_sel=1",
@@ -240,6 +270,7 @@
},
{
"BriefDescription": "Number of cores in C0",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"Filter": "occ_sel=2",
@@ -249,6 +280,7 @@
},
{
"BriefDescription": "Number of cores in C0",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"Filter": "occ_sel=3",
@@ -258,6 +290,7 @@
},
{
"BriefDescription": "External Prochot",
+ "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
@@ -266,6 +299,7 @@
},
{
"BriefDescription": "Internal Prochot",
+ "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
@@ -274,6 +308,7 @@
},
{
"BriefDescription": "Total Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -282,6 +317,7 @@
},
{
"BriefDescription": "Cycles Changing Voltage",
+ "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE",
"PerPkg": "1",
@@ -290,6 +326,7 @@
},
{
"BriefDescription": "Cycles Decreasing Voltage",
+ "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE",
"PerPkg": "1",
@@ -298,6 +335,7 @@
},
{
"BriefDescription": "Cycles Increasing Voltage",
+ "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE",
"PerPkg": "1",
@@ -306,6 +344,7 @@
},
{
"BriefDescription": "VR Hot",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
index fa08d355b97e..e0f6eb95455d 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
@@ -16,6 +18,7 @@
},
{
"BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -23,6 +26,7 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
@@ -31,6 +35,7 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
@@ -38,6 +43,7 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -45,6 +51,7 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -52,6 +59,7 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
@@ -59,6 +67,7 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
@@ -66,6 +75,7 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"SampleAfterValue": "100007",
@@ -73,6 +83,7 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
@@ -80,6 +91,7 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -87,6 +99,7 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -94,6 +107,7 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
@@ -102,6 +116,7 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries.",
+ "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"SampleAfterValue": "100007",
@@ -109,6 +124,7 @@
},
{
"BriefDescription": "STLB flush attempts.",
+ "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"SampleAfterValue": "100007",
--
2.45.2.627.g7a2c4fd464-goog
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