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Message-ID: <20240614034433.602622-10-liaochang1@huawei.com>
Date: Fri, 14 Jun 2024 03:44:32 +0000
From: Liao Chang <liaochang1@...wei.com>
To: <catalin.marinas@....com>, <will@...nel.org>, <ryabinin.a.a@...il.com>,
	<glider@...gle.com>, <andreyknvl@...il.com>, <dvyukov@...gle.com>,
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	<james.morse@....com>, <suzuki.poulose@....com>, <yuzenghui@...wei.com>,
	<mark.rutland@....com>, <lpieralisi@...nel.org>, <tglx@...utronix.de>,
	<ardb@...nel.org>, <broonie@...nel.org>, <liaochang1@...wei.com>,
	<steven.price@....com>, <ryan.roberts@....com>, <pcc@...gle.com>,
	<anshuman.khandual@....com>, <eric.auger@...hat.com>,
	<miguel.luis@...cle.com>, <shiqiliu@...t.edu.cn>, <quic_jiles@...cinc.com>,
	<rafael@...nel.org>, <sudeep.holla@....com>, <dwmw@...zon.co.uk>,
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	<scott@...amperecomputing.com>, <songshuaishuai@...ylab.org>,
	<swboyd@...omium.org>, <dianders@...omium.org>,
	<shijie@...amperecomputing.com>, <bhe@...hat.com>,
	<akpm@...ux-foundation.org>, <rppt@...nel.org>, <mhiramat@...nel.org>,
	<mcgrof@...nel.org>, <rmk+kernel@...linux.org.uk>,
	<Jonathan.Cameron@...wei.com>, <takakura@...inux.co.jp>,
	<sumit.garg@...aro.org>, <frederic@...nel.org>, <tabba@...gle.com>,
	<kristina.martsenko@....com>, <ruanjinjie@...wei.com>
CC: <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
	<kasan-dev@...glegroups.com>, <kvmarm@...ts.linux.dev>
Subject: [PATCH v4 09/10] arm64: irqchip/gic-v3: Simplify NMI handling in IRQs disabled context

After the recent refactoring to the exception entry code, the value of
PMR is not set to GIC_PRIO_IRQ_ON | GIC_PRIO_IRQ_I_SET unconditionally.
If kernel traps from IRQs disabled context, the PMR happens to
GIC_PRIO_IRQ_OFF, which allow only PESUDO_NMI could be acknowledged.
This patch leverage this fact to remove the unnecessary dropping of PMR
in NMI handler.

Signed-off-by: Liao Chang <liaochang1@...wei.com>
---
 arch/arm64/kernel/entry-common.c |  4 ++--
 drivers/irqchip/irq-gic-v3.c     | 23 +----------------------
 2 files changed, 3 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index eabfc80df6fb..fb3f5b772f57 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -531,6 +531,8 @@ static __always_inline void __el1_pnmi(struct pt_regs *regs,
 static __always_inline void __el1_irq(struct pt_regs *regs,
 				      void (*handler)(struct pt_regs *))
 {
+	local_nmi_disable();
+
 	enter_from_kernel_mode(regs);
 
 	irq_enter_rcu();
@@ -544,8 +546,6 @@ static __always_inline void __el1_irq(struct pt_regs *regs,
 static void noinstr el1_interrupt(struct pt_regs *regs,
 				  void (*handler)(struct pt_regs *))
 {
-	local_nmi_disable();
-
 	if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs))
 		__el1_pnmi(regs, handler);
 	else
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index ed7d8d87768f..de869051039b 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -831,28 +831,7 @@ static void __gic_handle_irq_from_irqson(struct pt_regs *regs)
  */
 static void __gic_handle_irq_from_irqsoff(struct pt_regs *regs)
 {
-	u64 pmr;
-	u32 irqnr;
-
-	/*
-	 * We were in a context with IRQs disabled. However, the
-	 * entry code has set PMR to a value that allows any
-	 * interrupt to be acknowledged, and not just NMIs. This can
-	 * lead to surprising effects if the NMI has been retired in
-	 * the meantime, and that there is an IRQ pending. The IRQ
-	 * would then be taken in NMI context, something that nobody
-	 * wants to debug twice.
-	 *
-	 * Until we sort this, drop PMR again to a level that will
-	 * actually only allow NMIs before reading IAR, and then
-	 * restore it to what it was.
-	 */
-	pmr = gic_read_pmr();
-	gic_pmr_mask_irqs();
-	isb();
-	irqnr = gic_read_iar();
-	gic_write_pmr(pmr);
-
+	u32 irqnr = gic_read_iar();
 	__gic_handle_nmi(irqnr, regs);
 }
 
-- 
2.34.1


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