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Message-Id: <20240614071932.1014067-3-claudiu.beznea.uj@bp.renesas.com>
Date: Fri, 14 Jun 2024 10:19:22 +0300
From: Claudiu <claudiu.beznea@...on.dev>
To: geert+renesas@...der.be,
mturquette@...libre.com,
sboyd@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
lee@...nel.org,
alexandre.belloni@...tlin.com,
magnus.damm@...il.com
Cc: linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-rtc@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
claudiu.beznea@...on.dev,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver
From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that feeds
the RTC and the tamper detector. Add documentation for the VBATTB clock
driver.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
---
.../clock/renesas,rzg3s-vbattb-clk.yaml | 90 +++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
new file mode 100644
index 000000000000..ef52a0c0f874
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,rzg3s-vbattb-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas VBATTB clock
+
+maintainers:
+ - Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
+
+description:
+ Renesas VBATTB module is an always on powered module (backed by battery) which
+ generates a clock (VBATTCLK). This clocks feeds the RTC and the tamper detector
+ modules.
+
+properties:
+ compatible:
+ const: renesas,rzg3s-vbattb-clk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: VBATTB module clock
+ - description: VBATTB input xtal
+
+ clock-names:
+ items:
+ - const: bclk
+ - const: vbattb_xtal
+
+ '#clock-cells':
+ const: 0
+
+ power-domains:
+ maxItems: 1
+
+ renesas,vbattb-load-nanofarads:
+ description: load capacitance of the on board xtal
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 4000, 7000, 9000, 12500 ]
+
+ renesas,vbattb-osc-bypass:
+ description: set when external clock is connected to RTXOUT pin
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - '#clock-cells'
+ - renesas,vbattb-load-nanofarads
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a08g045-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ vbattb: vbattb@...5c000 {
+ compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
+ reg = <0x1005c000 0x1000>;
+ ranges = <0 0 0x1005c000 0 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tampdi";
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
+ clock-names = "bclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_VBAT_BRESETN>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ vbattclk: clock-controller@1c {
+ compatible = "renesas,rzg3s-vbattb-clk";
+ reg = <0 0x1c 0 0x10>;
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
+ clock-names = "bclk", "vbattb_xtal";
+ #clock-cells = <0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+ };
+
+...
--
2.39.2
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