linux-kernel - Re: [PATCH v2 2/6] dt-bindings: riscv: Add Zicclsm ISA extension description.

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Message-ID: <20240614-broaden-bluish-8b2fe892db55@wendy>
Date: Fri, 14 Jun 2024 09:06:20 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: Jesse Taube <jesse@...osinc.com>
CC: <linux-riscv@...ts.infradead.org>, Jonathan Corbet <corbet@....net>, Paul
 Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Conor Dooley <conor@...nel.org>, Rob
 Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Clément Léger <cleger@...osinc.com>, Evan Green
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	<bjorn@...osinc.com>, Heiko Stuebner <heiko@...ech.de>, Costa Shulyupin
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	"Gustavo A. R. Silva" <gustavoars@...nel.org>, Erick Archer
	<erick.archer@....com>, Joel Granados <j.granados@...sung.com>,
	<linux-doc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 2/6] dt-bindings: riscv: Add Zicclsm ISA extension
 description.

On Thu, Jun 13, 2024 at 03:16:11PM -0400, Jesse Taube wrote:
> Add description for Zicclsm ISA extension.
> 
> Signed-off-by: Jesse Taube <jesse@...osinc.com>
> ---
> V1 -> V2:
>  - New patch
> ---
>  Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cfed80ad5540..9f6aae1f5b65 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -317,6 +317,13 @@ properties:
>              The standard Zicboz extension for cache-block zeroing as ratified
>              in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
>  
> +        - const: zicclsm
> +          description:
> +            The standard Zicclsm extension for misaligned support for all regular
> +            load and store instructions (including scalar and vector) but not AMOs
> +            or other specialized forms of memory access. Defined in the
> +            RISC-V RVA Profiles Specification.

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

> +
>          - const: zicntr
>            description:
>              The standard Zicntr extension for base counters and timers, as
> -- 
> 2.43.0
> 

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