linux-kernel - Re: [PATCH v2 4/6] RISC-V: Detect unaligned vector accesses supported.

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Message-ID: <20240614-viral-dinghy-71d5f6585a55@wendy>
Date: Fri, 14 Jun 2024 09:36:55 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: Jesse Taube <jesse@...osinc.com>
CC: <linux-riscv@...ts.infradead.org>, Jonathan Corbet <corbet@....net>, Paul
 Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Conor Dooley <conor@...nel.org>, Rob
 Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Clément Léger <cleger@...osinc.com>, Evan Green
	<evan@...osinc.com>, Andrew Jones <ajones@...tanamicro.com>, Charlie Jenkins
	<charlie@...osinc.com>, Xiao Wang <xiao.w.wang@...el.com>, Andy Chiu
	<andy.chiu@...ive.com>, Eric Biggers <ebiggers@...gle.com>, Greentime Hu
	<greentime.hu@...ive.com>, Björn Töpel
	<bjorn@...osinc.com>, Heiko Stuebner <heiko@...ech.de>, Costa Shulyupin
	<costa.shul@...hat.com>, Andrew Morton <akpm@...ux-foundation.org>, Baoquan
 He <bhe@...hat.com>, Anup Patel <apatel@...tanamicro.com>, Zong Li
	<zong.li@...ive.com>, Sami Tolvanen <samitolvanen@...gle.com>, Ben Dooks
	<ben.dooks@...ethink.co.uk>, Alexandre Ghiti <alexghiti@...osinc.com>,
	"Gustavo A. R. Silva" <gustavoars@...nel.org>, Erick Archer
	<erick.archer@....com>, Joel Granados <j.granados@...sung.com>,
	<linux-doc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 4/6] RISC-V: Detect unaligned vector accesses
 supported.

On Thu, Jun 13, 2024 at 03:16:13PM -0400, Jesse Taube wrote:
> --- a/arch/riscv/kernel/unaligned_access_speed.c
> +++ b/arch/riscv/kernel/unaligned_access_speed.c
> @@ -19,7 +19,8 @@
>  #define MISALIGNED_BUFFER_ORDER get_order(MISALIGNED_BUFFER_SIZE)
>  #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
>  
> -DEFINE_PER_CPU(long, misaligned_access_speed);
> +DEFINE_PER_CPU(long, misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
> +DEFINE_PER_CPU(long, vector_misaligned_access) = RISCV_HWPROBE_VEC_MISALIGNED_UNSUPPORTED;
>  
>  #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS
>  static cpumask_t fast_misaligned_access;
> @@ -268,12 +269,18 @@ static int check_unaligned_access_all_cpus(void)
>  
>  	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICCLSM)) {
>  		for_each_online_cpu(cpu) {
> +#ifdef CONFIG_RISCV_VECTOR_MISALIGNED
> +			per_cpu(vector_misaligned_access, cpu) = RISCV_HWPROBE_VEC_MISALIGNED_FAST;
> +#endif
> +#ifdef CONFIG_RISCV_MISALIGNED
>  			per_cpu(misaligned_access_speed, cpu) = RISCV_HWPROBE_MISALIGNED_FAST;
> +#endif

Can you IS_ENABLED()-ify these two as well please?

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