linux-kernel - [tip: irq/core] dt-bindings: interrupt-controller: Add support for Microchip LAN966x OIC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <171863226824.10875.13497028437531251336.tip-bot2@tip-bot2>
Date: Mon, 17 Jun 2024 13:51:08 -0000
From: "tip-bot2 for Herve Codina" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Herve Codina <herve.codina@...tlin.com>,
 Thomas Gleixner <tglx@...utronix.de>, "Rob Herring (Arm)" <robh@...nel.org>,
 x86@...nel.org, linux-kernel@...r.kernel.org, maz@...nel.org
Subject: [tip: irq/core] dt-bindings: interrupt-controller: Add support for
 Microchip LAN966x OIC

The following commit has been merged into the irq/core branch of tip:

Commit-ID:     17972a5f1ba85ad8c4f32dfd00ff620a85e98416
Gitweb:        https://git.kernel.org/tip/17972a5f1ba85ad8c4f32dfd00ff620a85e98416
Author:        Herve Codina <herve.codina@...tlin.com>
AuthorDate:    Fri, 14 Jun 2024 19:32:22 +02:00
Committer:     Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Mon, 17 Jun 2024 15:48:15 +02:00

dt-bindings: interrupt-controller: Add support for Microchip LAN966x OIC

The Microchip LAN966x outband interrupt controller (OIC) maps the
internal interrupt sources of the LAN966x device to an external
interrupt.
When the LAN966x device is used as a PCI device, the external interrupt
is routed to the PCI interrupt.

Signed-off-by: Herve Codina <herve.codina@...tlin.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
Link: https://lore.kernel.org/r/20240614173232.1184015-22-herve.codina@bootlin.com

---
 Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml b/Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml
new file mode 100644
index 0000000..b2adc71
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/microchip,lan966x-oic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip LAN966x outband interrupt controller
+
+maintainers:
+  - Herve Codina <herve.codina@...tlin.com>
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+  The Microchip LAN966x outband interrupt controller (OIC) maps the internal
+  interrupt sources of the LAN966x device to an external interrupt.
+  When the LAN966x device is used as a PCI device, the external interrupt is
+  routed to the PCI interrupt.
+
+properties:
+  compatible:
+    const: microchip,lan966x-oic
+
+  '#interrupt-cells':
+    const: 2
+
+  interrupt-controller: true
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - '#interrupt-cells'
+  - interrupt-controller
+  - interrupts
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    interrupt-controller@...c0120 {
+        compatible = "microchip,lan966x-oic";
+        reg = <0xe00c0120 0x190>;
+        #interrupt-cells = <2>;
+        interrupt-controller;
+        interrupts = <0>;
+        interrupt-parent = <&intc>;
+    };
+...