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Message-ID: <20240617005825.1443206-16-quic_gaurkash@quicinc.com>
Date: Sun, 16 Jun 2024 17:51:10 -0700
From: Gaurav Kashyap <quic_gaurkash@...cinc.com>
To: <linux-arm-msm@...r.kernel.org>, <linux-scsi@...r.kernel.org>,
<andersson@...nel.org>, <ebiggers@...gle.com>,
<neil.armstrong@...aro.org>, <srinivas.kandagatla@...aro.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<robh+dt@...nel.org>
CC: <linux-kernel@...r.kernel.org>, <linux-mmc@...r.kernel.org>,
<kernel@...cinc.com>, <linux-crypto@...r.kernel.org>,
<devicetree@...r.kernel.org>, <quic_omprsing@...cinc.com>,
<quic_nguyenb@...cinc.com>, <bartosz.golaszewski@...aro.org>,
<konrad.dybcio@...aro.org>, <ulf.hansson@...aro.org>,
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<psodagud@...cinc.com>, <quic_apurupa@...cinc.com>,
<sonalg@...cinc.com>, Gaurav Kashyap
<quic_gaurkash@...cinc.com>
Subject: [PATCH v5 15/15] arm64: dts: qcom: sm8550: add hwkm support to ufs ice
The Inline Crypto Engine (ICE) for UFS/EMMC supports the
Hardware Key Manager (HWKM) to securely manage storage
keys. Enable using this hardware on sm8550.
This requires two changes:
1. Register size increase: HWKM is an additional piece of hardware
sitting alongside ICE, and extends the old ICE's register space.
2. Explicitly tell the ICE driver to use HWKM with ICE so that
wrapped keys are used in sm8550.
NOTE: Although wrapped keys cannot be independently generated and
tested on this platform using generate, prepare and import key calls,
there are non-kernel paths to create wrapped keys, and still use the
kernel to program them into ICE. Hence, enabling wrapped key support
on sm8550 too.
Signed-off-by: Gaurav Kashyap <quic_gaurkash@...cinc.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index c55a818af935..a81f7d54d592 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2076,8 +2076,11 @@ opp-300000000 {
ice: crypto@...8000 {
compatible = "qcom,sm8550-inline-crypto-engine",
"qcom,inline-crypto-engine";
- reg = <0 0x01d88000 0 0x8000>;
+ reg = <0 0x01d88000 0 0x10000>;
+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+
+ qcom,ice-use-hwkm;
};
tcsr_mutex: hwlock@...0000 {
--
2.43.0
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