linux-kernel - Re: [PATCH v2 1/6] RISC-V: Add Zicclsm to cpufeature and hwprobe

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Message-ID: <CABgGipXKY0JPT8Z+U0g=KkFHFPyL3grd=1_GjQHNLbWehN-seg@mail.gmail.com>
Date: Mon, 17 Jun 2024 11:18:51 +0800
From: Andy Chiu <andy.chiu@...ive.com>
To: Conor Dooley <conor.dooley@...rochip.com>
Cc: Jesse Taube <jesse@...osinc.com>, linux-riscv@...ts.infradead.org, 
	Jonathan Corbet <corbet@....net>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Conor Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Clément Léger <cleger@...osinc.com>, 
	Evan Green <evan@...osinc.com>, Andrew Jones <ajones@...tanamicro.com>, 
	Charlie Jenkins <charlie@...osinc.com>, Xiao Wang <xiao.w.wang@...el.com>, 
	Eric Biggers <ebiggers@...gle.com>, Greentime Hu <greentime.hu@...ive.com>, 
	Björn Töpel <bjorn@...osinc.com>, 
	Heiko Stuebner <heiko@...ech.de>, Costa Shulyupin <costa.shul@...hat.com>, 
	Andrew Morton <akpm@...ux-foundation.org>, Baoquan He <bhe@...hat.com>, 
	Anup Patel <apatel@...tanamicro.com>, Zong Li <zong.li@...ive.com>, 
	Sami Tolvanen <samitolvanen@...gle.com>, Ben Dooks <ben.dooks@...ethink.co.uk>, 
	Alexandre Ghiti <alexghiti@...osinc.com>, "Gustavo A. R. Silva" <gustavoars@...nel.org>, 
	Erick Archer <erick.archer@....com>, Joel Granados <j.granados@...sung.com>, linux-doc@...r.kernel.org, 
	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v2 1/6] RISC-V: Add Zicclsm to cpufeature and hwprobe

On Fri, Jun 14, 2024 at 4:09 PM Conor Dooley <conor.dooley@...rochip.com> wrote:
>
> On Thu, Jun 13, 2024 at 03:16:10PM -0400, Jesse Taube wrote:
> > > Zicclsm Misaligned loads and stores to main memory regions with both
> > > the cacheability and coherence PMAs must be supported.
> > > Note:
> > > This introduces a new extension name for this feature.
> > > This requires misaligned support for all regular load and store
> > > instructions (including scalar and vector) but not AMOs or other
> > > specialized forms of memory access. Even though mandated, misaligned
> > > loads and stores might execute extremely slowly. Standard software
> > > distributions should assume their existence only for correctness,
> > > not for performance.
> >
> > Detecing zicclsm allows the kernel to report if the
> > hardware supports misaligned accesses even if support wasn't probed.
> >
> > This is useful for usermode to know if vector misaligned accesses are
> > supported.
> >
> > Signed-off-by: Jesse Taube <jesse@...osinc.com>
>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Reviewed-by: Andy Chiu <andy.chiu@...ive.com>