linux-kernel - Re: [PATCH 09/13] drm/mediatek: Fix XRGB setting error in OVL

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Message-ID: <d73bc79b3d80fc05db9430d04487ef463044a42a.camel@mediatek.com>
Date: Mon, 17 Jun 2024 08:02:11 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: Bibby Hsieh (謝濟遠) <Bibby.Hsieh@...iatek.com>,
	"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
	Shawn Sung (宋孝謙) <Shawn.Sung@...iatek.com>,
	"djkurtz@...omium.org" <djkurtz@...omium.org>,
	Nancy Lin (林欣螢) <Nancy.Lin@...iatek.com>,
	"daniel@...ll.ch" <daniel@...ll.ch>, "p.zabel@...gutronix.de"
	<p.zabel@...gutronix.de>, "airlied@...il.com" <airlied@...il.com>,
	YT Shen (沈岳霆) <Yt.Shen@...iatek.com>,
	"matthias.bgg@...il.com" <matthias.bgg@...il.com>, "littlecvr@...omium.org"
	<littlecvr@...omium.org>, "angelogioacchino.delregno@...labora.com"
	<angelogioacchino.delregno@...labora.com>
CC: "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
	"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 09/13] drm/mediatek: Fix XRGB setting error in OVL

Hi, Shawn:

On Sun, 2024-06-16 at 16:29 +0800, Hsiao Chien Sung via B4 Relay wrote:
>  	 
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>  From: Hsiao Chien Sung <shawn.sung@...iatek.com>
> 
> CONST_BLD must be enabled for XRGB formats although the alpha channel
> can be ignored, or OVL will still read the value from memory.
> This error only affects CRC generation.

Reviewed-by: CK Hu <ck.hu@...iatek.com>

> 
> Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
> Signed-off-by: Hsiao Chien Sung <shawn.sung@...iatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 738244a6164e..615b75919d1b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -38,6 +38,7 @@
>  #define DISP_REG_OVL_PITCH_MSB(n)(0x0040 + 0x20 * (n))
>  #define OVL_PITCH_MSB_2ND_SUBBUFBIT(16)
>  #define DISP_REG_OVL_PITCH(n)(0x0044 + 0x20 * (n))
> +#define OVL_CONST_BLENDBIT(28)
>  #define DISP_REG_OVL_RDMA_CTRL(n)(0x00c0 + 0x20 * (n))
>  #define DISP_REG_OVL_RDMA_GMC(n)(0x00c8 + 0x20 * (n))
>  #define DISP_REG_OVL_ADDR_MT27010x0040
> @@ -428,6 +429,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
>  unsigned int fmt = pending->format;
>  unsigned int offset = (pending->y << 16) | pending->x;
>  unsigned int src_size = (pending->height << 16) | pending->width;
> +unsigned int ignore_pixel_alpha = 0;
>  unsigned int con;
>  bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
>  union overlay_pitch {
> @@ -449,6 +451,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
>  if (state->base.fb && state->base.fb->format->has_alpha)
>  con |= OVL_CON_AEN | OVL_CON_ALPHA;
>  
> +/* CONST_BLD must be enabled for XRGB formats although the alpha channel
> + * can be ignored, or OVL will still read the value from memory.
> + * For RGB888 related formats, whether CONST_BLD is enabled or not won't
> + * affect the result. Therefore we use !has_alpha as the condition.
> + */
> +if (state->base.fb && !state->base.fb->format->has_alpha)
> +ignore_pixel_alpha = OVL_CONST_BLEND;
> +
>  if (pending->rotation & DRM_MODE_REFLECT_Y) {
>  con |= OVL_CON_VIRT_FLIP;
>  addr += (pending->height - 1) * pending->pitch;
> @@ -464,8 +474,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
>  
>  mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
>        DISP_REG_OVL_CON(idx));
> -mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,
> -      DISP_REG_OVL_PITCH(idx));
> +mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha,
> +      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
>  mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
>        DISP_REG_OVL_SRC_SIZE(idx));
>  mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
> 
> -- 
> Git-146)
> 
>