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Message-ID: <CAN6iL-Qz5--_bE=s8DKMtZFLJuNZca13ageGn48n4W7EKLUEUg@mail.gmail.com>
Date: Mon, 17 Jun 2024 15:57:04 +0530
From: Pranjal Shrivastava <praan@...gle.com>
To: Rob Clark <robdclark@...il.com>
Cc: iommu@...ts.linux.dev, linux-arm-msm@...r.kernel.org, 
	Stephen Boyd <swboyd@...omium.org>, Rob Clark <robdclark@...omium.org>, 
	Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>, Joerg Roedel <joro@...tes.org>, 
	Jason Gunthorpe <jgg@...pe.ca>, Jerry Snitselaar <jsnitsel@...hat.com>, 
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, 
	Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, 
	"moderated list:ARM SMMU DRIVERS" <linux-arm-kernel@...ts.infradead.org>, 
	open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] iommu/arm-smmu: Pretty-print context fault related regs

Hi Rob,
On Tue, Jun 4, 2024 at 8:32 PM Rob Clark <robdclark@...il.com> wrote:
>
> From: Rob Clark <robdclark@...omium.org>
>
> Parse out the bitfields for easier-to-read fault messages.
>
> Signed-off-by: Rob Clark <robdclark@...omium.org>
> ---
> Stephen was wanting easier to read fault messages.. so I typed this up.
>
> Resend with the new iommu list address
>
>  drivers/iommu/arm/arm-smmu/arm-smmu.c | 53 +++++++++++++++++++++++++--
>  drivers/iommu/arm/arm-smmu/arm-smmu.h |  5 +++
>  2 files changed, 54 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> index c572d877b0e1..06712d73519c 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> @@ -411,6 +411,8 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
>         unsigned long iova;
>         struct arm_smmu_domain *smmu_domain = dev;
>         struct arm_smmu_device *smmu = smmu_domain->smmu;
> +       static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
> +                                     DEFAULT_RATELIMIT_BURST);
>         int idx = smmu_domain->cfg.cbndx;
>         int ret;
>
> @@ -425,10 +427,53 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
>         ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
>                 fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
>
> -       if (ret == -ENOSYS)
> -               dev_err_ratelimited(smmu->dev,
> -               "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> -                           fsr, iova, fsynr, cbfrsynra, idx);
> +       if (ret == -ENOSYS && __ratelimit(&rs)) {
> +               static const struct {
> +                       u32 mask; const char *name;
> +               } fsr_bits[] = {
> +                       { ARM_SMMU_FSR_MULTI,  "MULTI" },
> +                       { ARM_SMMU_FSR_SS,     "SS"    },
> +                       { ARM_SMMU_FSR_UUT,    "UUT"   },
> +                       { ARM_SMMU_FSR_ASF,    "ASF"   },
> +                       { ARM_SMMU_FSR_TLBLKF, "TLBLKF" },
> +                       { ARM_SMMU_FSR_TLBMCF, "TLBMCF" },
> +                       { ARM_SMMU_FSR_EF,     "EF"     },
> +                       { ARM_SMMU_FSR_PF,     "PF"     },
> +                       { ARM_SMMU_FSR_AFF,    "AFF"    },
> +                       { ARM_SMMU_FSR_TF,     "TF"     },

I think we are missing to log the translation scheme i.e. `Format
bits[10:9]` field of this register as per the SMMUv2 spec. Maybe add
that too?

> +               }, fsynr0_bits[] = {
> +                       { ARM_SMMU_FSYNR0_WNR,    "WNR"    },
> +                       { ARM_SMMU_FSYNR0_PNU,    "PNU"    },
> +                       { ARM_SMMU_FSYNR0_IND,    "IND"    },
> +                       { ARM_SMMU_FSYNR0_NSATTR, "NSATTR" },
> +                       { ARM_SMMU_FSYNR0_PTWF,   "PTWF"   },
> +                       { ARM_SMMU_FSYNR0_AFR,    "AFR"    },
> +               };
> +
> +               pr_err("%s %s: Unhandled context fault: fsr=0x%x (",
> +                      dev_driver_string(smmu->dev), dev_name(smmu->dev), fsr);
> +
> +               for (int i = 0, n = 0; i < ARRAY_SIZE(fsr_bits); i++) {
> +                       if (fsr & fsr_bits[i].mask) {
> +                               pr_cont("%s%s", (n > 0) ? "|" : "", fsr_bits[i].name);
> +                               n++;
> +                       }
> +               }

Nit: Maybe add a line-wrap here after logging the iova?
Not trying to sound like a terminal geek, but a full log with pr_cont
could get very long (> 80 characters).
So, let's log fsr & iova in one line, fsynr and others in the next.

> +
> +               pr_cont("), iova=0x%08lx, fsynr=0x%x (S1CBNDX=%u", iova, fsynr,
> +                       (fsynr >> 16) & 0xff);
> +
> +               for (int i = 0; i < ARRAY_SIZE(fsynr0_bits); i++) {
> +                       if (fsynr & fsynr0_bits[i].mask) {
> +                               pr_cont("|%s", fsynr0_bits[i].name);
> +                       }
> +               }
> +
> +               pr_cont("|PLVL=%u), cbfrsynra=0x%x, cb=%d\n",
> +                       fsynr & 0x3,   /* FSYNR0.PLV */
> +                       cbfrsynra, idx);
> +
> +       }
>
>         arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
>         return IRQ_HANDLED;
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> index 836ed6799a80..3b051273718b 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> @@ -223,6 +223,11 @@ enum arm_smmu_cbar_type {
>
>  #define ARM_SMMU_CB_FSYNR0             0x68
>  #define ARM_SMMU_FSYNR0_WNR            BIT(4)
> +#define ARM_SMMU_FSYNR0_PNU            BIT(5)
> +#define ARM_SMMU_FSYNR0_IND            BIT(6)
> +#define ARM_SMMU_FSYNR0_NSATTR         BIT(8)
> +#define ARM_SMMU_FSYNR0_PTWF           BIT(10)
> +#define ARM_SMMU_FSYNR0_AFR            BIT(11)
>

Nit: Worth prefixing these with "CB_" i.e. "ARM_SMMU_CB_FSYNR0_* " to
avoid confusion with "GFSYNR0".

>  #define ARM_SMMU_CB_FSYNR1             0x6c
>
> --
> 2.45.1
>
>
Thanks,
Pranjal

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