lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Mon, 17 Jun 2024 15:04:02 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Aradhya Bhatia <a-bhatia1@...com>
Cc: Tomi Valkeinen <tomi.valkeinen@...asonboard.com>, 
	Andrzej Hajda <andrzej.hajda@...el.com>, Neil Armstrong <neil.armstrong@...aro.org>, 
	Robert Foss <rfoss@...nel.org>, Laurent Pinchart <Laurent.pinchart@...asonboard.com>, 
	Jonas Karlman <jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>, 
	Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>, 
	Jyri Sarha <jyri.sarha@....fi>, Thomas Zimmermann <tzimmermann@...e.de>, 
	David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>, 
	DRI Development List <dri-devel@...ts.freedesktop.org>, Linux Kernel List <linux-kernel@...r.kernel.org>, 
	Dominik Haller <d.haller@...tec.de>, Sam Ravnborg <sam@...nborg.org>, 
	Thierry Reding <treding@...dia.com>, Kieran Bingham <kieran.bingham+renesas@...asonboard.com>, 
	Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>, 
	Praneeth Bajjuri <praneeth@...com>, Udit Kumar <u-kumar1@...com>, Devarsh Thakkar <devarsht@...com>, 
	Jayesh Choudhary <j-choudhary@...com>, Jai Luthra <j-luthra@...com>
Subject: Re: [PATCH v3 06/10] drm/bridge: cdns-dsi: Reset the DCS write FIFO

On Mon, Jun 17, 2024 at 04:23:07PM GMT, Aradhya Bhatia wrote:
> Allow the DCS Write FIFO in the cdns-dsi controller to reset before any
> DCS packet is transmitted to the DSI sink device.
> 
> The DCS FIFO reset is optional. Not all panels require it. But at
> least one of the DSI based panel that uses Ilitek ILI9881C (DSI to DPI
> bridge) doesn't work with without this reset.

Could you please be more specific, why doesn't it work. Are there any
leftover bytes in the FIFO? Is there any additional delay?

> 
> Signed-off-by: Aradhya Bhatia <a-bhatia1@...com>
> ---
>  drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> index 05d2f4cc50da..87fdd07ca0bc 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> @@ -1037,6 +1037,9 @@ static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
>  
>  	cdns_dsi_init_link(dsi);
>  
> +	/* Reset the DCS Write FIFO */
> +	writel(0x00, dsi->regs + DIRECT_CMD_FIFO_RST);
> +
>  	ret = mipi_dsi_create_packet(&packet, msg);
>  	if (ret)
>  		goto out;
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ