linux-kernel - Re: [PATCH v2 3/9] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L

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Message-ID: <CAMuHMdUgbnFoHWsB8NPu+Whn+FBkQ_EogS3yH+g-1wGTxensgQ@mail.gmail.com>
Date: Mon, 17 Jun 2024 14:15:29 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Paul Barker <paul.barker.ct@...renesas.com>
Cc: Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Linus Walleij <linus.walleij@...aro.org>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, linux-renesas-soc@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-gpio@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/9] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L

Hi Paul,

On Tue, Jun 11, 2024 at 1:33 PM Paul Barker
<paul.barker.ct@...renesas.com> wrote:
> On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK
> signal is selectable to support an Ethernet PHY operating in either MII
> or RGMII mode. By default, the signal is configured as an input and MII
> mode is supported. The ETH_MODE register can be modified to configure
> this signal as an output to support RGMII mode.
>
> As this signal is by default an input, and can optionally be switched to
> an output, it maps neatly onto an `output-enable` property in the device
> tree.
>
> Signed-off-by: Paul Barker <paul.barker.ct@...renesas.com>
> ---
> Changes v1->v2:
>   * Use oen_read and oen_write function pointers to be compatible with
>     recent patches adding RZ/V2H support.

Thanks for your patch!

> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -994,6 +994,61 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
>         return false;
>  }
>
> +static int rzg2l_pin_to_oen_bit(const struct rzg2l_hwcfg *hwcfg, u32 caps,
> +                               u32 port, u8 pin)
> +{
> +       if (!(caps & PIN_CFG_OEN) || pin > hwcfg->oen_max_pin)
> +               return -EINVAL;
> +
> +       /*
> +        * We can determine which Ethernet interface we're dealing with from
> +        * the caps.
> +        */
> +       if (caps & PIN_CFG_IO_VMC_ETH0)
> +               return 0;
> +       if (caps & PIN_CFG_IO_VMC_ETH1)
> +               return 1;
> +
> +       return -EINVAL;
> +}
> +
> +static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, unsigned int _pin)

rzg2l_oen_read()

> +{
> +       u32 port = RZG2L_PIN_ID_TO_PORT(_pin);
> +       u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
> +       int bit;
> +
> +       bit = rzg2l_pin_to_oen_bit(pctrl->data->hwcfg, caps, port, pin);
> +       if (bit < 0)
> +               return 0;
> +
> +       return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
> +}
> +
> +static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, unsigned int _pin, u8 oen)

rzg2l_oen_write()

With these fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds