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Message-ID: <20240618072726.3767974-4-quic_jiegan@quicinc.com>
Date: Tue, 18 Jun 2024 15:27:26 +0800
From: Jie Gan <quic_jiegan@...cinc.com>
To: Mathieu Poirier <mathieu.poirier@...aro.org>,
Suzuki K Poulose
<suzuki.poulose@....com>,
Alexander Shishkin
<alexander.shishkin@...ux.intel.com>,
Konrad Dybcio <konradybcio@...il.com>,
Mike Leach <mike.leach@...aro.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC: Jinlong Mao <quic_jinlmao@...cinc.com>,
Greg Kroah-Hartman
<gregkh@...uxfoundation.org>,
<coresight@...ts.linaro.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
Tingwei Zhang <quic_tingweiz@...cinc.com>,
Yuanfang Zhang <quic_yuanfang@...cinc.com>,
Tao Zhang
<quic_taozha@...cinc.com>,
Trilok Soni <quic_tsoni@...cinc.com>,
Song Chai
<quic_songchai@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <andersson@...nel.org>,
<quic_yijiyang@...cinc.com>, <quic_yuanjiey@...cinc.com>,
<quic_liuxin@...cinc.com>, <quic_yanzl@...cinc.com>,
<quic_xinlon@...cinc.com>, <quic_xueqnie@...cinc.com>,
<quic_sijiwu@...cinc.com>
Subject: [PATCH v1 3/3] arm64: dts: qcom: Add CSR and ETR nodes for SA8775p
Add CSR and ETR device tree nodes to enable related functions.
Signed-off-by: Jie Gan <quic_jiegan@...cinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 167 ++++++++++++++++++++++++++
1 file changed, 167 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 839c6ec0a957..1154d456c239 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -1657,6 +1657,36 @@ ice: crypto@...8000 {
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
+ csr: csr@...1000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x0 0x4001000 0x0 0x1000>;
+ reg-names = "csr-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ csr_in0: endpoint {
+ remote-endpoint =
+ <&etr0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ csr_in1: endpoint {
+ remote-endpoint =
+ <&etr1_out>;
+ };
+ };
+ };
+ };
+
stm: stm@...2000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x4002000 0x0 0x1000>,
@@ -1860,6 +1890,135 @@ qdss_funnel_in1: endpoint {
};
};
+ replicator@...6000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x4046000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ qdss_rep_out0: endpoint {
+ remote-endpoint =
+ <&etr_rep_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ qdss_rep_in: endpoint {
+ remote-endpoint =
+ <&swao_rep_out0>;
+ };
+ };
+ };
+ };
+
+ tmc_etr: tmc@...8000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x4048000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04c0 0x00>;
+
+ arm,scatter-gather;
+ qcom,csr-atid-offset = <0xf8>;
+
+ out-ports {
+ port {
+ etr0_out: endpoint {
+ remote-endpoint =
+ <&csr_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etr0_in: endpoint {
+ remote-endpoint =
+ <&etr_rep_out0>;
+ };
+ };
+ };
+ };
+
+ replicator@...e000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x404e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ etr_rep_out0: endpoint {
+ remote-endpoint =
+ <&etr0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ etr_rep_out1: endpoint {
+ remote-endpoint =
+ <&etr1_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etr_rep_in: endpoint {
+ remote-endpoint =
+ <&qdss_rep_out0>;
+ };
+ };
+ };
+ };
+
+ tmc_etr1: tmc@...f000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x404f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04a0 0x40>;
+
+ arm,scatter-gather;
+ arm,buffer-size = <0x400000>;
+ qcom,csr-atid-offset = <0x108>;
+
+ out-ports {
+ port {
+ etr1_out: endpoint {
+ remote-endpoint =
+ <&csr_in1>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etr1_in: endpoint {
+ remote-endpoint =
+ <&etr_rep_out1>;
+ };
+ };
+ };
+ };
+
funnel@...4000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x4b04000 0x0 0x1000>;
@@ -1935,6 +2094,14 @@ out-ports {
#address-cells = <1>;
#size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ swao_rep_out0: endpoint {
+ remote-endpoint =
+ <&qdss_rep_in>;
+ };
+ };
+
port@1 {
reg = <1>;
swao_rep_out1: endpoint {
--
2.34.1
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