linux-kernel - Re: [PATCH 0/6] riscv: convert bottom half of exception handling to C

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Wed, 19 Jun 2024 09:30:10 -0700
From: Deepak Gupta <debug@...osinc.com>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Samuel Holland <samuel.holland@...ive.com>,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/6] riscv: convert bottom half of exception handling to C

On Mon, Jun 17, 2024 at 01:05:47AM +0800, Jisheng Zhang wrote:
>For readability, maintainability and future scalability, convert the
>bottom half of the exception handling to C.
>
>During the conversion, I found Anton fixed a performance issue
>and my patches will touch the same exception asm code, so I include
>Anton's patch for completeness. I also cooked a similar patch to avoid
>corrupting the RAS in ret_from_fork() per the inspiration.

nit: Probably corruption is wrong word here giving the notion that software
got some capability to corrupt uarch structures. It's simply mismatched # of
call and # of rets. Imbalance (instead of calling it corruption) in return
address stack (RAS) leading to incorret predictions on return.

>
>Mostly the assembly code is converted to C in a relatively
>straightforward manner.
>
>However, there are two modifications I need to mention:
>
>1. the CSR_CAUSE reg reading and saving is moved to the C code
>because we need the cause to dispatch the exception handling,
>if we keep the cause reading and saving, we either pass it to
>do_traps() via. 2nd param or get it from pt_regs which an extra
>memory load is needed, I don't like any of the two solutions becase
>the exception handling sits in hot code path, every instruction
>matters.
>
>2.To cope with SIFIVE_CIP_453 errata, it looks like we don't need
>alternative mechanism any more after the asm->c convertion. Just
>replace the excp_vect_table two entries.
>
>
>
>Anton Blanchard (1):
>  riscv: Improve exception and system call latency
>
>Jisheng Zhang (5):
>  riscv: avoid corrupting the RAS
>  riscv: convert bottom half of exception handling to C
>  riscv: errata: remove ALT_INSN_FAULT and ALT_PAGE_FAULT
>  riscv: errata: sifive: remove NOMMU handling
>  riscv: remove asmlinkage from updated functions
>
> arch/riscv/errata/sifive/errata.c         | 25 +++++++---
> arch/riscv/errata/sifive/errata_cip_453.S |  4 --
> arch/riscv/include/asm/asm-prototypes.h   |  7 +--
> arch/riscv/include/asm/errata_list.h      | 21 ++------
> arch/riscv/kernel/entry.S                 | 61 ++---------------------
> arch/riscv/kernel/stacktrace.c            |  4 +-
> arch/riscv/kernel/traps.c                 | 57 ++++++++++++++++++---
> 7 files changed, 81 insertions(+), 98 deletions(-)
>
>-- 
>2.43.0
>
>