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Message-ID: <24b58c63-95c9-43d4-a5cb-78754c94cbfb@oracle.com>
Date: Wed, 19 Jun 2024 08:59:33 +0100
From: John Garry <john.g.garry@...cle.com>
To: Keith Busch <kbusch@...nel.org>
Cc: Christoph Hellwig <hch@....de>, axboe@...nel.dk, sagi@...mberg.me,
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Himanshu Madhani <himanshu.madhani@...cle.com>
Subject: Re: [PATCH v8 05/10] block: Add core atomic write support
On 18/06/2024 18:25, Keith Busch wrote:
> On Tue, Jun 18, 2024 at 08:46:31AM +0100, John Garry wrote:
>> About NVMe, the spec says that NABSN and NOIOB may not be related to one
>> another (command set spec 1.0d 5.8.2.1), but I am wondering if people really
>> build HW which would have different NABSN/NABSPF and NOIOB. I don't know.
> The history of NOIOB is from an nvme drive that had two back-end
> controllers with their own isolated storage, and then striped together
> on the front end for the host to see. A command crossing the stripe
> boundary takes a slow path to split it for each backend controller's
> portion and merge the results. Subsequent implementations may have
> different reasons for advertising this boundary, but that was the
> original.
In this case, I would expect NOIOB >= atomic write boundary.
Would it be sane to have a NOIOB < atomic write boundary in some other
config?
I can support these possibilities, but the code will just get more complex.
>
> Anyway, there was an idea that the stripe size could be user
> configurable, though that never shipped as far as I know. If it had,
> then the optimal NOIOB could be made larger, but the atomic write size
> doesn't change.
Thanks,
John
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