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Message-ID: <20240619085322.66716-1-angelogioacchino.delregno@collabora.com>
Date: Wed, 19 Jun 2024 10:53:20 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: krzk+dt@...nel.org
Cc: mturquette@...libre.com,
sboyd@...nel.org,
robh@...nel.org,
conor+dt@...nel.org,
matthias.bgg@...il.com,
angelogioacchino.delregno@...labora.com,
jassisinghbrar@...il.com,
garmin.chang@...iatek.com,
houlong.wei@...iatek.com,
Jason-ch.Chen@...iatek.com,
amergnat@...libre.com,
Elvis.Wang@...iatek.com,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
kernel@...labora.com
Subject: [PATCH 1/3] arm64: dts: mediatek: mt8188: Fix VPPSYS0/1 node name/compatibles
Like VDOSYS0/1, the VPPSYS0 and VPPSYS1 are syscon nodes, as
described by the mediatek,mmsys binding: fix the node name to
be syscon@...ress and add "syscon" to the list of compatible
strings for both VPPSYS0 and VPPSYS1.
Fixes: 9461e0caac9e ("arm64: dts: Add MediaTek MT8188 dts and evaluation board and Makefile")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 3b02170562ae..77c4f2d104cd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1331,8 +1331,8 @@ mfgcfg: clock-controller@...bf000 {
#clock-cells = <1>;
};
- vppsys0: clock-controller@...00000 {
- compatible = "mediatek,mt8188-vppsys0";
+ vppsys0: syscon@...00000 {
+ compatible = "mediatek,mt8188-vppsys0", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
@@ -1349,8 +1349,8 @@ wpesys_vpp0: clock-controller@...02000 {
#clock-cells = <1>;
};
- vppsys1: clock-controller@...00000 {
- compatible = "mediatek,mt8188-vppsys1";
+ vppsys1: syscon@...00000 {
+ compatible = "mediatek,mt8188-vppsys1", "syscon";
reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>;
};
--
2.45.2
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