linux-kernel - [PATCH 1/1] iommu/vt-d: Fix missed device TLB cache tag

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Message-Id: <20240619015345.182773-1-baolu.lu@linux.intel.com>
Date: Wed, 19 Jun 2024 09:53:45 +0800
From: Lu Baolu <baolu.lu@...ux.intel.com>
To: Joerg Roedel <joro@...tes.org>,
	Will Deacon <will@...nel.org>,
	Robin Murphy <robin.murphy@....com>,
	Kevin Tian <kevin.tian@...el.com>,
	Jacek Lawrynowicz <jacek.lawrynowicz@...ux.intel.com>
Cc: iommu@...ts.linux.dev,
	linux-kernel@...r.kernel.org,
	Lu Baolu <baolu.lu@...ux.intel.com>
Subject: [PATCH 1/1] iommu/vt-d: Fix missed device TLB cache tag

When a domain is attached to a device, the required cache tags are
assigned to the domain so that the related caches could be flushed
whenever it is needed. The device TLB cache tag is created selectively 
by checking the ats_enabled field of the device's iommu data. This
creates an ordered dependency between attach and ATS enabling paths.

The device TLB cache tag will not be created if device's ATS is enabled
after the domain attachment. This causes some devices, for example
intel_vpu, to malfunction.

Create device TLB cache tags for a domain as long as the ats_supported
field of the attached device is true. In the cache invalidation paths,
the ats_enable field is checked and the device TLB invalidation requests
are issued only when the ATS is really enabled on the device.

Fixes: 3b1d9e2b2d68 ("iommu/vt-d: Add cache tag assignment interface")
Signed-off-by: Lu Baolu <baolu.lu@...ux.intel.com>
---
 drivers/iommu/intel/cache.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c
index e8418cdd8331..ec6770f556b9 100644
--- a/drivers/iommu/intel/cache.c
+++ b/drivers/iommu/intel/cache.c
@@ -112,7 +112,7 @@ static int __cache_tag_assign_domain(struct dmar_domain *domain, u16 did,
 	int ret;
 
 	ret = cache_tag_assign(domain, did, dev, pasid, CACHE_TAG_IOTLB);
-	if (ret || !info->ats_enabled)
+	if (ret || !info->ats_supported)
 		return ret;
 
 	ret = cache_tag_assign(domain, did, dev, pasid, CACHE_TAG_DEVTLB);
@@ -129,7 +129,7 @@ static void __cache_tag_unassign_domain(struct dmar_domain *domain, u16 did,
 
 	cache_tag_unassign(domain, did, dev, pasid, CACHE_TAG_IOTLB);
 
-	if (info->ats_enabled)
+	if (info->ats_supported)
 		cache_tag_unassign(domain, did, dev, pasid, CACHE_TAG_DEVTLB);
 }
 
@@ -140,7 +140,7 @@ static int __cache_tag_assign_parent_domain(struct dmar_domain *domain, u16 did,
 	int ret;
 
 	ret = cache_tag_assign(domain, did, dev, pasid, CACHE_TAG_NESTING_IOTLB);
-	if (ret || !info->ats_enabled)
+	if (ret || !info->ats_supported)
 		return ret;
 
 	ret = cache_tag_assign(domain, did, dev, pasid, CACHE_TAG_NESTING_DEVTLB);
@@ -157,7 +157,7 @@ static void __cache_tag_unassign_parent_domain(struct dmar_domain *domain, u16 d
 
 	cache_tag_unassign(domain, did, dev, pasid, CACHE_TAG_NESTING_IOTLB);
 
-	if (info->ats_enabled)
+	if (info->ats_supported)
 		cache_tag_unassign(domain, did, dev, pasid, CACHE_TAG_NESTING_DEVTLB);
 }
 
@@ -309,6 +309,9 @@ void cache_tag_flush_range(struct dmar_domain *domain, unsigned long start,
 			info = dev_iommu_priv_get(tag->dev);
 			sid = PCI_DEVID(info->bus, info->devfn);
 
+			if (!info->ats_enabled)
+				break;
+
 			if (tag->pasid == IOMMU_NO_PASID)
 				qi_flush_dev_iotlb(iommu, sid, info->pfsid,
 						   info->ats_qdep, addr, mask);
@@ -356,6 +359,9 @@ void cache_tag_flush_all(struct dmar_domain *domain)
 			info = dev_iommu_priv_get(tag->dev);
 			sid = PCI_DEVID(info->bus, info->devfn);
 
+			if (!info->ats_enabled)
+				break;
+
 			qi_flush_dev_iotlb(iommu, sid, info->pfsid, info->ats_qdep,
 					   0, MAX_AGAW_PFN_WIDTH);
 			quirk_extra_dev_tlb_flush(info, 0, MAX_AGAW_PFN_WIDTH,
-- 
2.34.1