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Message-Id: <20240619120920.2703605-4-claudiu.beznea.uj@bp.renesas.com>
Date: Wed, 19 Jun 2024 15:09:20 +0300
From: Claudiu <claudiu.beznea@...on.dev>
To: ulf.hansson@...aro.org,
wim@...ux-watchdog.org,
linux@...ck-us.net,
rafael@...nel.org
Cc: linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-watchdog@...r.kernel.org,
claudiu.beznea@...on.dev,
geert+renesas@...der.be,
linux-renesas-soc@...r.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: [PATCH RFC 3/3] watchdog: rzg2l_wdt: Power on the PM domain in rzg2l_wdt_restart()
From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
The rzg2l_wdt_restart() is called in atomic context. Calling
pm_runtime_{get_sync, resume_and_get}() or any other runtime PM resume
APIs is not an option as it may lead to issues as described in commit
e4cf89596c1f ("watchdog: rzg2l_wdt: Fix 'BUG: Invalid wait context'")
that removed the pm_runtime_get_sync() and enabled directly the clocks.
Starting with RZ/G3S the watchdog could be part of its own
software-controlled power domain. In case the watchdog is not used the
power domain is off and accessing watchdog registers leads to aborts.
To solve this, the patch powers on the power domain using
dev_pm_genpd_resume_restart_dev() API after enabling its clock. This is
not sleeping or taking any other locks as the watchdog power domain is not
registered with GENPD_FLAG_IRQ_SAFE flags.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
---
drivers/watchdog/rzg2l_wdt.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c
index 6e3d7512f38c..bbdbbaa7b82b 100644
--- a/drivers/watchdog/rzg2l_wdt.c
+++ b/drivers/watchdog/rzg2l_wdt.c
@@ -12,6 +12,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/units.h>
@@ -169,6 +170,17 @@ static int rzg2l_wdt_restart(struct watchdog_device *wdev,
clk_enable(priv->pclk);
clk_enable(priv->osc_clk);
+ /*
+ * The device may be part of a power domain that is currently
+ * powered off. We need to power it on before accessing registers.
+ * We don't undo the dev_pm_genpd_resume_restart_dev() as the device
+ * need to be on for the reboot to happen. Also, as we are in atomic
+ * context here, there is no need to increment PM runtime usage counter
+ * (to make sure pm_runtime_active() doesn't return wrong code).
+ */
+ if (!pm_runtime_active(wdev->parent))
+ dev_pm_genpd_resume_restart_dev(wdev->parent);
+
if (priv->devtype == WDT_RZG2L) {
ret = reset_control_deassert(priv->rstc);
if (ret)
--
2.39.2
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