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Message-ID: <20240619-opp_support-v15-2-aa769a2173a3@quicinc.com>
Date: Wed, 19 Jun 2024 20:41:11 +0530
From: Krishna chaitanya chundru <quic_krichai@...cinc.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
"Lorenzo
Pieralisi" <lpieralisi@...nel.org>,
Krzysztof WilczyĆski
<kw@...ux.com>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas
<bhelgaas@...gle.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>
CC: <quic_vbadigan@...cinc.com>, <quic_skananth@...cinc.com>,
<quic_nitegupt@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>,
Krishna chaitanya chundru
<quic_krichai@...cinc.com>,
Krzysztof Kozlowski <krzk@...nel.org>
Subject: [PATCH v15 2/4] dt-bindings: pci: qcom: Add OPP table
PCIe needs to choose the appropriate performance state of RPMh power
domain based on the PCIe gen speed.
Adding the Operating Performance Points table allows to adjust power
domain performance state and ICC peak bw, depending on the PCIe data
rate and link width.
Reviewed-by: Krzysztof Kozlowski <krzk@...nel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
---
Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
index 1496d6993ab4..d8c0afaa4b19 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
@@ -69,6 +69,10 @@ properties:
- const: msi6
- const: msi7
+ operating-points-v2: true
+ opp-table:
+ type: object
+
resets:
maxItems: 1
--
2.42.0
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