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Message-ID: <x3jznckxbnqz6lxbqpdgmevw7dppsuqiqs56vugeyxhbcmw2m4@fyk6mzrtg5b7>
Date: Thu, 20 Jun 2024 18:16:18 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Varadarajan Narayanan <quic_varada@...cinc.com>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
angelogioacchino.delregno@...labora.com, andersson@...nel.org, konrad.dybcio@...aro.org,
mturquette@...libre.com, sboyd@...nel.org, ulf.hansson@...aro.org, quic_sibis@...cinc.com,
quic_rjendra@...cinc.com, luca@...tu.xyz, abel.vesa@...aro.org, quic_rohiagar@...cinc.com,
danila@...xyga.com, otto.pflueger@...cue.de, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
linux-pm@...r.kernel.org
Subject: Re: [PATCH v1 7/7] dts: arm64: qcom: ipq9574: Enable CPR
On Thu, Jun 20, 2024 at 01:44:27PM GMT, Varadarajan Narayanan wrote:
> Add CPR, RPMPD, OPP table nodes as applicable to IPQ9574 to
> enable CPR functionality on IPQ9574.
Please document your CPU opp table changes in the commit message. You
have added 792 MHz, dropped 1200 MHz. At least we need to know what's
going on.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 269 ++++++++++++++++++++++++--
> 1 file changed, 252 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 04ba09a9156c..439ee5accc47 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -11,6 +11,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> #include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
>
> / {
> interrupt-parent = <&intc>;
> @@ -42,8 +43,9 @@ CPU0: cpu@0 {
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq9574_s1>;
> #cooling-cells = <2>;
> + power-domains = <&apc_cprh 0>;
> + power-domain-names = "perf";
> };
>
> CPU1: cpu@1 {
> @@ -55,8 +57,9 @@ CPU1: cpu@1 {
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq9574_s1>;
> #cooling-cells = <2>;
> + power-domains = <&apc_cprh 0>;
> + power-domain-names = "perf";
> };
>
> CPU2: cpu@2 {
> @@ -68,8 +71,9 @@ CPU2: cpu@2 {
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq9574_s1>;
> #cooling-cells = <2>;
> + power-domains = <&apc_cprh 0>;
> + power-domain-names = "perf";
> };
>
> CPU3: cpu@3 {
> @@ -81,8 +85,9 @@ CPU3: cpu@3 {
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq9574_s1>;
> #cooling-cells = <2>;
> + power-domains = <&apc_cprh 0>;
> + power-domain-names = "perf";
> };
>
> L2_0: l2-cache {
> @@ -105,58 +110,111 @@ memory@...00000 {
> reg = <0x0 0x40000000 0x0 0x0>;
> };
>
> + cprh_opp_table: opp-table-cprh {
> + compatible = "operating-points-v2-qcom-level";
> +
> + cprh_opp0: opp-0 {
> + opp-level = <1>;
> + qcom,opp-fuse-level = <1>;
> + qcom,opp-cloop-vadj = <0>;
> + qcom,opp-oloop-vadj = <0>;
> + };
> +
> + cprh_opp1: opp-1 {
> + opp-level = <2>;
> + qcom,opp-fuse-level = <1>;
> + qcom,opp-cloop-vadj = <0>;
> + qcom,opp-oloop-vadj = <0>;
> + };
> +
> + cprh_opp2: opp-2 {
> + opp-level = <3>;
> + qcom,opp-fuse-level = <1>;
> + qcom,opp-cloop-vadj = <0>;
> + qcom,opp-oloop-vadj = <0>;
> + };
> +
> + cprh_opp3: opp-3 {
> + opp-level = <4>;
> + qcom,opp-fuse-level = <2>;
> + qcom,opp-cloop-vadj = <0>;
> + qcom,opp-oloop-vadj = <0>;
> + };
> +
> + cprh_opp4: opp-4 {
> + opp-level = <5>;
> + qcom,opp-fuse-level = <2>;
> + qcom,opp-cloop-vadj = <0>;
> + qcom,opp-oloop-vadj = <0>;
> + };
> +
> + cprh_opp5: opp-5 {
> + opp-level = <6>;
> + qcom,opp-fuse-level = <3>;
> + qcom,opp-cloop-vadj = <0>;
> + qcom,opp-oloop-vadj = <0>;
> + };
> +
> + cprh_opp6: opp-6 {
> + opp-level = <7>;
> + qcom,opp-fuse-level = <4>;
> + qcom,opp-cloop-vadj = <0>;
> + qcom,opp-oloop-vadj = <0>;
> + };
> + };
> +
> cpu_opp_table: opp-table-cpu {
> compatible = "operating-points-v2-kryo-cpu";
> opp-shared;
> nvmem-cells = <&cpu_speed_bin>;
>
> + opp-792000000 {
> + opp-hz = /bits/ 64 <792000000>;
> + opp-supported-hw = <0x0>;
> + clock-latency-ns = <200000>;
> + required-opps = <&cprh_opp0>;
> + };
> +
> opp-936000000 {
> opp-hz = /bits/ 64 <936000000>;
> - opp-microvolt = <725000>;
> opp-supported-hw = <0xf>;
> clock-latency-ns = <200000>;
> + required-opps = <&cprh_opp1>;
> };
>
> opp-1104000000 {
> opp-hz = /bits/ 64 <1104000000>;
> - opp-microvolt = <787500>;
> - opp-supported-hw = <0xf>;
> - clock-latency-ns = <200000>;
> - };
> -
> - opp-1200000000 {
> - opp-hz = /bits/ 64 <1200000000>;
> - opp-microvolt = <862500>;
> opp-supported-hw = <0xf>;
> clock-latency-ns = <200000>;
> + required-opps = <&cprh_opp2>;
> };
>
> opp-1416000000 {
> opp-hz = /bits/ 64 <1416000000>;
> - opp-microvolt = <862500>;
> opp-supported-hw = <0x7>;
> clock-latency-ns = <200000>;
> + required-opps = <&cprh_opp3>;
> };
>
> opp-1488000000 {
> opp-hz = /bits/ 64 <1488000000>;
> - opp-microvolt = <925000>;
> opp-supported-hw = <0x7>;
> clock-latency-ns = <200000>;
> + required-opps = <&cprh_opp4>;
> };
>
> opp-1800000000 {
> opp-hz = /bits/ 64 <1800000000>;
> - opp-microvolt = <987500>;
> opp-supported-hw = <0x5>;
> clock-latency-ns = <200000>;
> + required-opps = <&cprh_opp5>;
> };
>
> opp-2208000000 {
> opp-hz = /bits/ 64 <2208000000>;
> - opp-microvolt = <1062500>;
> opp-supported-hw = <0x1>;
> clock-latency-ns = <200000>;
> + required-opps = <&cprh_opp6>;
> };
> };
>
> @@ -182,6 +240,40 @@ glink-edge {
> rpm_requests: rpm-requests {
> compatible = "qcom,rpm-ipq9574";
> qcom,glink-channels = "rpm_requests";
> +
> + rpmpd: power-controller {
> + compatible = "qcom,ipq9574-rpmpd";
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&rpmpd_opp_table>;
> +
> + rpmpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmpd_opp_svs: opp1 {
Where are these nodes going to be used?
> + opp-level = <RPM_SMD_LEVEL_SVS>;
> + };
> +
> + rpmpd_opp_svs_plus: opp2 {
> + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
> + };
> +
> + rpmpd_opp_nom: opp3 {
> + opp-level = <RPM_SMD_LEVEL_NOM>;
> + };
> +
> + rpmpd_opp_nom_plus: opp4 {
> + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
> + };
> +
> + rpmpd_opp_turbo: opp5 {
> + opp-level = <RPM_SMD_LEVEL_TURBO>;
> + };
> +
> + rpmpd_opp_turbo_high: opp6 {
> + opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
> + };
> + };
> + };
> };
> };
> };
> @@ -252,6 +344,95 @@ cpu_speed_bin: cpu-speed-bin@15 {
> reg = <0x15 0x2>;
> bits = <7 2>;
> };
> +
> + cpr_efuse_speedbin: speedbin@5 {
> + reg = <0x5 0x8>;
> + bits = <0 3>;
> + };
> +
> + cpr_fuse_revision: cpr-fusing-rev@7 {
> + reg = <0x7 0x8>;
> + bits = <1 5>;
> + };
> +
> + /* CPR Ring Oscillator: Power Cluster */
> + cpr_ro_sel0_pwrcl: rosel0-pwrcl@358 { /* ROSEL_SVS */
> + reg = <0x358 0x1>;
> + bits = <4 4>;
> + };
> +
> + cpr_ro_sel1_pwrcl: rosel1-pwrcl@358 { /* ROSEL_NOM */
> + reg = <0x358 0x1>;
> + bits = <0 4>;
> + };
> +
> + cpr_ro_sel2_pwrcl: rosel2-pwrcl@350 { /* ROSEL_TUR */
> + reg = <0x350 0x1>;
> + bits = <4 4>;
> + };
> +
> + cpr_ro_sel3_pwrcl: rosel3-pwrcl@350 { /* ROSEL_STUR */
> + reg = <0x350 0x1>;
> + bits = <0 4>;
> + };
> +
> + /* CPR Init Voltage: Power Cluster */
> + cpr_init_voltage0_pwrcl: ivolt0-pwrcl@343 { /* VOLT_SVS */
> + reg = <0x343 0x1>;
> + bits = <0 6>;
> + };
> +
> + cpr_init_voltage1_pwrcl: ivolt1-pwrcl@342 { /* VOLT_NOM */
> + reg = <0x342 0x1>;
> + bits = <2 6>;
> + };
> +
> + cpr_init_voltage2_pwrcl: ivolt2-pwrcl@341 { /* VOLT_TUR */
> + reg = <0x341 0x2>;
> + bits = <4 6>;
> + };
> +
> + cpr_init_voltage3_pwrcl: ivolt3-pwrcl@340 { /* VOLT_STUR */
> + reg = <0x340 0x2>;
> + bits = <6 6>;
> + };
> +
> + /* CPR Target Quotients: Power Cluster */
> + cpr_quot0_pwrcl: quot0-pwrcl@354 { /* QUOT_VMIN_SVS */
> + reg = <0x354 0x2>;
> + bits = <0 12>;
> + };
> +
> + cpr_quot1_pwrcl: quot1-pwrcl@352 { /* QUOT_VMIN_NOM */
> + reg = <0x352 0x2>;
> + bits = <4 12>;
> + };
> +
> + cpr_quot2_pwrcl: quot2-pwrcl@351 { /* QUOT_VMIN_TUR */
> + reg = <0x351 0x2>;
> + bits = <0 12>;
> + };
> +
> + cpr_quot3_pwrcl: quot3-pwrcl@355 { /* QUOT_VMIN_STUR */
> + reg = <0x355 0x2>;
> + bits = <4 12>;
> + };
> +
> + /* CPR Quotient Offsets: Power Cluster */
> + cpr_quot_offset1_pwrcl: qoff1-pwrcl@34e { /* QUOT_OFFSET_NOM_SVS */
> + reg = <0x34e 0x1>;
> + bits = <0 8>;
> + };
> +
> + cpr_quot_offset2_pwrcl: qoff2-pwrcl@34d { /* QUOT_OFFSET_TUR_NOM */
> + reg = <0x34d 0x1>;
> + bits = <0 8>;
> + };
> +
> + cpr_quot_offset3_pwrcl: qoff0-pwrcl@34c { /* QUOT_OFFSET_STUR_TUR */
> + reg = <0x34c 0x1>;
> + bits = <0 8>;
> + };
> };
>
> cryptobam: dma-controller@...000 {
> @@ -639,6 +820,60 @@ usb_0_dwc3: usb@...0000 {
> };
> };
>
> + apc_cprh: power-controller@...8000 {
> + compatible = "qcom,ipq9574-cprh", "qcom,cprh";
> + reg = <0x0b018000 0x4000>,
> + <0x00048000 0x4000>;
> +
> + clocks = <&gcc GCC_RBCPR_CLK>;
> +
> + interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
> + vdd-supply = <&ipq9574_s1>;
> +
> + /* Set the CPR clock here, it needs to match XO */
> + assigned-clocks = <&gcc GCC_RBCPR_CLK>;
> + assigned-clock-rates = <24000000>;
> +
> + operating-points-v2 = <&cprh_opp_table>;
> + power-domains = <&rpmpd IPQ9574_VDDAPC>;
> + #power-domain-cells = <1>;
> +
> + nvmem-cells = <&cpr_efuse_speedbin>,
> + <&cpr_fuse_revision>,
> + <&cpr_quot0_pwrcl>,
> + <&cpr_quot1_pwrcl>,
> + <&cpr_quot2_pwrcl>,
> + <&cpr_quot3_pwrcl>,
> + <&cpr_quot_offset1_pwrcl>,
> + <&cpr_quot_offset2_pwrcl>,
> + <&cpr_quot_offset3_pwrcl>,
> + <&cpr_init_voltage0_pwrcl>,
> + <&cpr_init_voltage1_pwrcl>,
> + <&cpr_init_voltage2_pwrcl>,
> + <&cpr_init_voltage3_pwrcl>,
> + <&cpr_ro_sel0_pwrcl>,
> + <&cpr_ro_sel1_pwrcl>,
> + <&cpr_ro_sel2_pwrcl>,
> + <&cpr_ro_sel3_pwrcl>;
> + nvmem-cell-names = "cpr_speed_bin",
> + "cpr_fuse_revision",
> + "cpr0_quotient1",
> + "cpr0_quotient2",
> + "cpr0_quotient3",
> + "cpr0_quotient4",
> + "cpr0_quotient_offset2",
> + "cpr0_quotient_offset3",
> + "cpr0_quotient_offset4",
> + "cpr0_init_voltage1",
> + "cpr0_init_voltage2",
> + "cpr0_init_voltage3",
> + "cpr0_init_voltage4",
> + "cpr0_ring_osc1",
> + "cpr0_ring_osc2",
> + "cpr0_ring_osc3",
> + "cpr0_ring_osc4";
> + };
> +
> intc: interrupt-controller@...0000 {
> compatible = "qcom,msm-qgic2";
> reg = <0x0b000000 0x1000>, /* GICD */
> --
> 2.34.1
>
--
With best wishes
Dmitry
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