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Message-Id: <20240620161622.3986692-4-Frank.Li@nxp.com>
Date: Thu, 20 Jun 2024 12:16:22 -0400
From: Frank Li <Frank.Li@....com>
To: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS),
imx@...ts.linux.dev (open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE),
linux-arm-kernel@...ts.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE),
linux-kernel@...r.kernel.org (open list)
Subject: [PATCH v2 4/4] arm64: dts: imx95-19x19-evk: add PCIe[0,1] support
Add PCIe[0,1] and all dependent nodes.
Signed-off-by: Frank Li <Frank.Li@....com>
---
Change from v1 to v2
- remove regulator-always-on
---
.../boot/dts/freescale/imx95-19x19-evk.dts | 56 +++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 750a5255b57ce..d14a54ab4fd47 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -40,6 +40,34 @@ linux_cma: linux,cma {
};
};
+ reg_m2_pwr: regulator-m2-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "M.2-power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_pcie0: regulator-pcie {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE_WLAN_EN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_m2_pwr>;
+ gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_slot_pwr: regulator-slot-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIe slot-power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -84,6 +112,22 @@ &mu7 {
status = "okay";
};
+&pcie0 {
+ pinctrl-0 = <&pinctrl_pcie0>;
+ pinctrl-names = "default";
+ reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcie0>;
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-0 = <&pinctrl_pcie1>;
+ pinctrl-names = "default";
+ reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_slot_pwr>;
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -128,6 +172,18 @@ IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e
>;
};
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e
+ >;
+ };
+
+ pinctrl_pcie1: pcie1grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
--
2.34.1
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