| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 20 Jun 2024 11:17:39 -0700
From: Ian Rogers <irogers@...gle.com>
To: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>, Jiri Olsa <jolsa@...nel.org>,
Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>,
Kan Liang <kan.liang@...ux.intel.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org
Cc: Weilin Wang <weilin.wang@...el.com>, Caleb Biggers <caleb.biggers@...el.com>
Subject: [PATCH v2 25/37] perf vendor events: Add nehalemex counter information
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@...el.com>
Co-authored-by: Caleb Biggers <caleb.biggers@...el.com>
Signed-off-by: Ian Rogers <irogers@...gle.com>
Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>
---
.../pmu-events/arch/x86/nehalemex/cache.json | 315 ++++++++++++++++++
.../arch/x86/nehalemex/counter.json | 7 +
.../arch/x86/nehalemex/floating-point.json | 28 ++
.../arch/x86/nehalemex/frontend.json | 3 +
.../pmu-events/arch/x86/nehalemex/memory.json | 67 ++++
.../pmu-events/arch/x86/nehalemex/other.json | 18 +
.../arch/x86/nehalemex/pipeline.json | 109 ++++++
.../arch/x86/nehalemex/virtual-memory.json | 13 +
8 files changed, 560 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/x86/nehalemex/counter.json
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json b/tools/perf/pmu-events/arch/x86/nehalemex/cache.json
index 0042e53fdc78..2c0ea6f8c4e0 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/cache.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Cycles L1D locked",
+ "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D",
"SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Cycles L1D and L2 locked",
+ "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
"SampleAfterValue": "2000000",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "L1D cache lines replaced in M state",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_EVICT",
"SampleAfterValue": "2000000",
@@ -22,6 +25,7 @@
},
{
"BriefDescription": "L1D cache lines allocated in the M state",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_REPL",
"SampleAfterValue": "2000000",
@@ -29,6 +33,7 @@
},
{
"BriefDescription": "L1D snoop eviction of cache lines in M state",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_SNOOP_EVICT",
"SampleAfterValue": "2000000",
@@ -36,6 +41,7 @@
},
{
"BriefDescription": "L1 data cache lines allocated",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.REPL",
"SampleAfterValue": "2000000",
@@ -43,6 +49,7 @@
},
{
"BriefDescription": "All references to the L1 data cache",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "L1D_ALL_REF.ANY",
"SampleAfterValue": "2000000",
@@ -50,6 +57,7 @@
},
{
"BriefDescription": "L1 data cacheable reads and writes",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "L1D_ALL_REF.CACHEABLE",
"SampleAfterValue": "2000000",
@@ -57,6 +65,7 @@
},
{
"BriefDescription": "L1 data cache read in E state",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.E_STATE",
"SampleAfterValue": "2000000",
@@ -64,6 +73,7 @@
},
{
"BriefDescription": "L1 data cache read in I state (misses)",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.I_STATE",
"SampleAfterValue": "2000000",
@@ -71,6 +81,7 @@
},
{
"BriefDescription": "L1 data cache reads",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.MESI",
"SampleAfterValue": "2000000",
@@ -78,6 +89,7 @@
},
{
"BriefDescription": "L1 data cache read in M state",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.M_STATE",
"SampleAfterValue": "2000000",
@@ -85,6 +97,7 @@
},
{
"BriefDescription": "L1 data cache read in S state",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.S_STATE",
"SampleAfterValue": "2000000",
@@ -92,6 +105,7 @@
},
{
"BriefDescription": "L1 data cache load locks in E state",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.E_STATE",
"SampleAfterValue": "2000000",
@@ -99,6 +113,7 @@
},
{
"BriefDescription": "L1 data cache load lock hits",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.HIT",
"SampleAfterValue": "2000000",
@@ -106,6 +121,7 @@
},
{
"BriefDescription": "L1 data cache load locks in M state",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.M_STATE",
"SampleAfterValue": "2000000",
@@ -113,6 +129,7 @@
},
{
"BriefDescription": "L1 data cache load locks in S state",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.S_STATE",
"SampleAfterValue": "2000000",
@@ -120,6 +137,7 @@
},
{
"BriefDescription": "L1D load lock accepted in fill buffer",
+ "Counter": "0,1",
"EventCode": "0x53",
"EventName": "L1D_CACHE_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -127,6 +145,7 @@
},
{
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
+ "Counter": "0,1",
"EventCode": "0x52",
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -134,6 +153,7 @@
},
{
"BriefDescription": "L1 data cache stores in E state",
+ "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.E_STATE",
"SampleAfterValue": "2000000",
@@ -141,6 +161,7 @@
},
{
"BriefDescription": "L1 data cache stores in M state",
+ "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.M_STATE",
"SampleAfterValue": "2000000",
@@ -148,6 +169,7 @@
},
{
"BriefDescription": "L1 data cache stores in S state",
+ "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.S_STATE",
"SampleAfterValue": "2000000",
@@ -155,6 +177,7 @@
},
{
"BriefDescription": "L1D hardware prefetch misses",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.MISS",
"SampleAfterValue": "200000",
@@ -162,6 +185,7 @@
},
{
"BriefDescription": "L1D hardware prefetch requests",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.REQUESTS",
"SampleAfterValue": "200000",
@@ -169,6 +193,7 @@
},
{
"BriefDescription": "L1D hardware prefetch requests triggered",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.TRIGGERS",
"SampleAfterValue": "200000",
@@ -176,6 +201,7 @@
},
{
"BriefDescription": "L1 writebacks to L2 in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.E_STATE",
"SampleAfterValue": "100000",
@@ -183,6 +209,7 @@
},
{
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.I_STATE",
"SampleAfterValue": "100000",
@@ -190,6 +217,7 @@
},
{
"BriefDescription": "All L1 writebacks to L2",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.MESI",
"SampleAfterValue": "100000",
@@ -197,6 +225,7 @@
},
{
"BriefDescription": "L1 writebacks to L2 in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.M_STATE",
"SampleAfterValue": "100000",
@@ -204,6 +233,7 @@
},
{
"BriefDescription": "L1 writebacks to L2 in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.S_STATE",
"SampleAfterValue": "100000",
@@ -211,6 +241,7 @@
},
{
"BriefDescription": "All L2 data requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.ANY",
"SampleAfterValue": "200000",
@@ -218,6 +249,7 @@
},
{
"BriefDescription": "L2 data demand loads in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@@ -225,6 +257,7 @@
},
{
"BriefDescription": "L2 data demand loads in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@@ -232,6 +265,7 @@
},
{
"BriefDescription": "L2 data demand requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
"SampleAfterValue": "200000",
@@ -239,6 +273,7 @@
},
{
"BriefDescription": "L2 data demand loads in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@@ -246,6 +281,7 @@
},
{
"BriefDescription": "L2 data demand loads in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@@ -253,6 +289,7 @@
},
{
"BriefDescription": "L2 data prefetches in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@@ -260,6 +297,7 @@
},
{
"BriefDescription": "L2 data prefetches in the I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@@ -267,6 +305,7 @@
},
{
"BriefDescription": "All L2 data prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
"SampleAfterValue": "200000",
@@ -274,6 +313,7 @@
},
{
"BriefDescription": "L2 data prefetches in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@@ -281,6 +321,7 @@
},
{
"BriefDescription": "L2 data prefetches in the S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@@ -288,6 +329,7 @@
},
{
"BriefDescription": "L2 lines allocated",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ANY",
"SampleAfterValue": "100000",
@@ -295,6 +337,7 @@
},
{
"BriefDescription": "L2 lines allocated in the E state",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E_STATE",
"SampleAfterValue": "100000",
@@ -302,6 +345,7 @@
},
{
"BriefDescription": "L2 lines allocated in the S state",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S_STATE",
"SampleAfterValue": "100000",
@@ -309,6 +353,7 @@
},
{
"BriefDescription": "L2 lines evicted",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.ANY",
"SampleAfterValue": "100000",
@@ -316,6 +361,7 @@
},
{
"BriefDescription": "L2 lines evicted by a demand request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100000",
@@ -323,6 +369,7 @@
},
{
"BriefDescription": "L2 modified lines evicted by a demand request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100000",
@@ -330,6 +377,7 @@
},
{
"BriefDescription": "L2 lines evicted by a prefetch request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
"SampleAfterValue": "100000",
@@ -337,6 +385,7 @@
},
{
"BriefDescription": "L2 modified lines evicted by a prefetch request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
"SampleAfterValue": "100000",
@@ -344,6 +393,7 @@
},
{
"BriefDescription": "L2 instruction fetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCHES",
"SampleAfterValue": "200000",
@@ -351,6 +401,7 @@
},
{
"BriefDescription": "L2 instruction fetch hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_HIT",
"SampleAfterValue": "200000",
@@ -358,6 +409,7 @@
},
{
"BriefDescription": "L2 instruction fetch misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_MISS",
"SampleAfterValue": "200000",
@@ -365,6 +417,7 @@
},
{
"BriefDescription": "L2 load hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_HIT",
"SampleAfterValue": "200000",
@@ -372,6 +425,7 @@
},
{
"BriefDescription": "L2 load misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_MISS",
"SampleAfterValue": "200000",
@@ -379,6 +433,7 @@
},
{
"BriefDescription": "L2 requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LOADS",
"SampleAfterValue": "200000",
@@ -386,6 +441,7 @@
},
{
"BriefDescription": "All L2 misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200000",
@@ -393,6 +449,7 @@
},
{
"BriefDescription": "All L2 prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCHES",
"SampleAfterValue": "200000",
@@ -400,6 +457,7 @@
},
{
"BriefDescription": "L2 prefetch hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_HIT",
"SampleAfterValue": "200000",
@@ -407,6 +465,7 @@
},
{
"BriefDescription": "L2 prefetch misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_MISS",
"SampleAfterValue": "200000",
@@ -414,6 +473,7 @@
},
{
"BriefDescription": "All L2 requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200000",
@@ -421,6 +481,7 @@
},
{
"BriefDescription": "L2 RFO requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFOS",
"SampleAfterValue": "200000",
@@ -428,6 +489,7 @@
},
{
"BriefDescription": "L2 RFO hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200000",
@@ -435,6 +497,7 @@
},
{
"BriefDescription": "L2 RFO misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200000",
@@ -442,6 +505,7 @@
},
{
"BriefDescription": "All L2 transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.ANY",
"SampleAfterValue": "200000",
@@ -449,6 +513,7 @@
},
{
"BriefDescription": "L2 fill transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.FILL",
"SampleAfterValue": "200000",
@@ -456,6 +521,7 @@
},
{
"BriefDescription": "L2 instruction fetch transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.IFETCH",
"SampleAfterValue": "200000",
@@ -463,6 +529,7 @@
},
{
"BriefDescription": "L1D writeback to L2 transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.L1D_WB",
"SampleAfterValue": "200000",
@@ -470,6 +537,7 @@
},
{
"BriefDescription": "L2 Load transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.LOAD",
"SampleAfterValue": "200000",
@@ -477,6 +545,7 @@
},
{
"BriefDescription": "L2 prefetch transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.PREFETCH",
"SampleAfterValue": "200000",
@@ -484,6 +553,7 @@
},
{
"BriefDescription": "L2 RFO transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.RFO",
"SampleAfterValue": "200000",
@@ -491,6 +561,7 @@
},
{
"BriefDescription": "L2 writeback to LLC transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.WB",
"SampleAfterValue": "200000",
@@ -498,6 +569,7 @@
},
{
"BriefDescription": "L2 demand lock RFOs in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.E_STATE",
"SampleAfterValue": "100000",
@@ -505,6 +577,7 @@
},
{
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.HIT",
"SampleAfterValue": "100000",
@@ -512,6 +585,7 @@
},
{
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.I_STATE",
"SampleAfterValue": "100000",
@@ -519,6 +593,7 @@
},
{
"BriefDescription": "All demand L2 lock RFOs",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.MESI",
"SampleAfterValue": "100000",
@@ -526,6 +601,7 @@
},
{
"BriefDescription": "L2 demand lock RFOs in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.M_STATE",
"SampleAfterValue": "100000",
@@ -533,6 +609,7 @@
},
{
"BriefDescription": "L2 demand lock RFOs in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.S_STATE",
"SampleAfterValue": "100000",
@@ -540,6 +617,7 @@
},
{
"BriefDescription": "All L2 demand store RFOs that hit the cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.HIT",
"SampleAfterValue": "100000",
@@ -547,6 +625,7 @@
},
{
"BriefDescription": "L2 demand store RFOs in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.I_STATE",
"SampleAfterValue": "100000",
@@ -554,6 +633,7 @@
},
{
"BriefDescription": "All L2 demand store RFOs",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.MESI",
"SampleAfterValue": "100000",
@@ -561,6 +641,7 @@
},
{
"BriefDescription": "L2 demand store RFOs in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.M_STATE",
"SampleAfterValue": "100000",
@@ -568,6 +649,7 @@
},
{
"BriefDescription": "L2 demand store RFOs in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.S_STATE",
"SampleAfterValue": "100000",
@@ -575,6 +657,7 @@
},
{
"BriefDescription": "Longest latency cache miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100000",
@@ -582,6 +665,7 @@
},
{
"BriefDescription": "Longest latency cache reference",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "200000",
@@ -589,6 +673,7 @@
},
{
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
"MSRIndex": "0x3F6",
@@ -598,6 +683,7 @@
},
{
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
"MSRIndex": "0x3F6",
@@ -608,6 +694,7 @@
},
{
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
"MSRIndex": "0x3F6",
@@ -618,6 +705,7 @@
},
{
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
"MSRIndex": "0x3F6",
@@ -628,6 +716,7 @@
},
{
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
"MSRIndex": "0x3F6",
@@ -638,6 +727,7 @@
},
{
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
"MSRIndex": "0x3F6",
@@ -648,6 +738,7 @@
},
{
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
"MSRIndex": "0x3F6",
@@ -658,6 +749,7 @@
},
{
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
"MSRIndex": "0x3F6",
@@ -668,6 +760,7 @@
},
{
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
"MSRIndex": "0x3F6",
@@ -678,6 +771,7 @@
},
{
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
"MSRIndex": "0x3F6",
@@ -688,6 +782,7 @@
},
{
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
"MSRIndex": "0x3F6",
@@ -698,6 +793,7 @@
},
{
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
"MSRIndex": "0x3F6",
@@ -708,6 +804,7 @@
},
{
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
"MSRIndex": "0x3F6",
@@ -718,6 +815,7 @@
},
{
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
"MSRIndex": "0x3F6",
@@ -728,6 +826,7 @@
},
{
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
"MSRIndex": "0x3F6",
@@ -738,6 +837,7 @@
},
{
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LOADS",
"PEBS": "1",
@@ -746,6 +846,7 @@
},
{
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.STORES",
"PEBS": "1",
@@ -754,6 +855,7 @@
},
{
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -762,6 +864,7 @@
},
{
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
"PEBS": "1",
@@ -770,6 +873,7 @@
},
{
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
@@ -778,6 +882,7 @@
},
{
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -786,6 +891,7 @@
},
{
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
"PEBS": "1",
@@ -794,6 +900,7 @@
},
{
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
"PEBS": "1",
@@ -802,6 +909,7 @@
},
{
"BriefDescription": "Offcore L1 data cache writebacks",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
"SampleAfterValue": "100000",
@@ -809,6 +917,7 @@
},
{
"BriefDescription": "Offcore requests blocked due to Super Queue full",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
"SampleAfterValue": "100000",
@@ -816,6 +925,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -825,6 +935,7 @@
},
{
"BriefDescription": "All offcore data reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -834,6 +945,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -843,6 +955,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -852,6 +965,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -861,6 +975,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -870,6 +985,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -879,6 +995,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -888,6 +1005,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -897,6 +1015,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -906,6 +1025,7 @@
},
{
"BriefDescription": "Offcore data reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -915,6 +1035,7 @@
},
{
"BriefDescription": "Offcore data reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -924,6 +1045,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -933,6 +1055,7 @@
},
{
"BriefDescription": "All offcore code reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -942,6 +1065,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -951,6 +1075,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -960,6 +1085,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -969,6 +1095,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -978,6 +1105,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -987,6 +1115,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -996,6 +1125,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1005,6 +1135,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1014,6 +1145,7 @@
},
{
"BriefDescription": "Offcore code reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1023,6 +1155,7 @@
},
{
"BriefDescription": "Offcore code reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1032,6 +1165,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1041,6 +1175,7 @@
},
{
"BriefDescription": "All offcore requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1050,6 +1185,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1059,6 +1195,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1068,6 +1205,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1077,6 +1215,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1086,6 +1225,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1095,6 +1235,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1104,6 +1245,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1113,6 +1255,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1122,6 +1265,7 @@
},
{
"BriefDescription": "Offcore requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1131,6 +1275,7 @@
},
{
"BriefDescription": "Offcore requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1140,6 +1285,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1149,6 +1295,7 @@
},
{
"BriefDescription": "All offcore RFO requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1158,6 +1305,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1167,6 +1315,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1176,6 +1325,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1185,6 +1335,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1194,6 +1345,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1203,6 +1355,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1212,6 +1365,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1221,6 +1375,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1230,6 +1385,7 @@
},
{
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1239,6 +1395,7 @@
},
{
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1248,6 +1405,7 @@
},
{
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1257,6 +1415,7 @@
},
{
"BriefDescription": "All offcore writebacks",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1266,6 +1425,7 @@
},
{
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1275,6 +1435,7 @@
},
{
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1284,6 +1445,7 @@
},
{
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1293,6 +1455,7 @@
},
{
"BriefDescription": "Offcore writebacks to the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1302,6 +1465,7 @@
},
{
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1311,6 +1475,7 @@
},
{
"BriefDescription": "Offcore writebacks to a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1320,6 +1485,7 @@
},
{
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1329,6 +1495,7 @@
},
{
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1338,6 +1505,7 @@
},
{
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1347,6 +1515,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1356,6 +1525,7 @@
},
{
"BriefDescription": "All offcore code or data read requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1365,6 +1535,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1374,6 +1545,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1383,6 +1555,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1392,6 +1565,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1401,6 +1575,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1410,6 +1585,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1419,6 +1595,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1428,6 +1605,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1437,6 +1615,7 @@
},
{
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1446,6 +1625,7 @@
},
{
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1455,6 +1635,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = any cache_dram",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1464,6 +1645,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = any location",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1473,6 +1655,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1482,6 +1665,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1491,6 +1675,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1500,6 +1685,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1509,6 +1695,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = local cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1518,6 +1705,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = local cache or dram",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1527,6 +1715,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1536,6 +1725,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1545,6 +1735,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1554,6 +1745,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1563,6 +1755,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1572,6 +1765,7 @@
},
{
"BriefDescription": "All offcore demand data requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1581,6 +1775,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1590,6 +1785,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1599,6 +1795,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1608,6 +1805,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1617,6 +1815,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1626,6 +1825,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1635,6 +1835,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1644,6 +1845,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1653,6 +1855,7 @@
},
{
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1662,6 +1865,7 @@
},
{
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1671,6 +1875,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1680,6 +1885,7 @@
},
{
"BriefDescription": "All offcore demand data reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1689,6 +1895,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1698,6 +1905,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1707,6 +1915,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1716,6 +1925,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1725,6 +1935,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1734,6 +1945,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1743,6 +1955,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1752,6 +1965,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1761,6 +1975,7 @@
},
{
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1770,6 +1985,7 @@
},
{
"BriefDescription": "Offcore demand data reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1779,6 +1995,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1788,6 +2005,7 @@
},
{
"BriefDescription": "All offcore demand code reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1797,6 +2015,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1806,6 +2025,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1815,6 +2035,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1824,6 +2045,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1833,6 +2055,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1842,6 +2065,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1851,6 +2075,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1860,6 +2085,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1869,6 +2095,7 @@
},
{
"BriefDescription": "Offcore demand code reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1878,6 +2105,7 @@
},
{
"BriefDescription": "Offcore demand code reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1887,6 +2115,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1896,6 +2125,7 @@
},
{
"BriefDescription": "All offcore demand RFO requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1905,6 +2135,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1914,6 +2145,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1923,6 +2155,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1932,6 +2165,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1941,6 +2175,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1950,6 +2185,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1959,6 +2195,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1968,6 +2205,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1977,6 +2215,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1986,6 +2225,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1995,6 +2235,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2004,6 +2245,7 @@
},
{
"BriefDescription": "All offcore other requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2013,6 +2255,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2022,6 +2265,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2031,6 +2275,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2040,6 +2285,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2049,6 +2295,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2058,6 +2305,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2067,6 +2315,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2076,6 +2325,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2085,6 +2335,7 @@
},
{
"BriefDescription": "Offcore other requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2094,6 +2345,7 @@
},
{
"BriefDescription": "Offcore other requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2103,6 +2355,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2112,6 +2365,7 @@
},
{
"BriefDescription": "All offcore prefetch data requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2121,6 +2375,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2130,6 +2385,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2139,6 +2395,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2148,6 +2405,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2157,6 +2415,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2166,6 +2425,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2175,6 +2435,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2184,6 +2445,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2193,6 +2455,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2202,6 +2465,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2211,6 +2475,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2220,6 +2485,7 @@
},
{
"BriefDescription": "All offcore prefetch data reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2229,6 +2495,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2238,6 +2505,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2247,6 +2515,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2256,6 +2525,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2265,6 +2535,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2274,6 +2545,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2283,6 +2555,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2292,6 +2565,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2301,6 +2575,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2310,6 +2585,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2319,6 +2595,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2328,6 +2605,7 @@
},
{
"BriefDescription": "All offcore prefetch code reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2337,6 +2615,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2346,6 +2625,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2355,6 +2635,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2364,6 +2645,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2373,6 +2655,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2382,6 +2665,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2391,6 +2675,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2400,6 +2685,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2409,6 +2695,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2418,6 +2705,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2427,6 +2715,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2436,6 +2725,7 @@
},
{
"BriefDescription": "All offcore prefetch RFO requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2445,6 +2735,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2454,6 +2745,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2463,6 +2755,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2472,6 +2765,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2481,6 +2775,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2490,6 +2785,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2499,6 +2795,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2508,6 +2805,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2517,6 +2815,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2526,6 +2825,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2535,6 +2835,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2544,6 +2845,7 @@
},
{
"BriefDescription": "All offcore prefetch requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2553,6 +2855,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2562,6 +2865,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2571,6 +2875,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2580,6 +2885,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2589,6 +2895,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2598,6 +2905,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2607,6 +2915,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2616,6 +2925,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2625,6 +2935,7 @@
},
{
"BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2634,6 +2945,7 @@
},
{
"BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2643,6 +2955,7 @@
},
{
"BriefDescription": "Super Queue lock splits across a cache line",
+ "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "2000000",
@@ -2650,6 +2963,7 @@
},
{
"BriefDescription": "Loads delayed with at-Retirement block code",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.AT_RET",
"SampleAfterValue": "200000",
@@ -2657,6 +2971,7 @@
},
{
"BriefDescription": "Cacheable loads delayed with L1D block code",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.L1D_BLOCK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/counter.json b/tools/perf/pmu-events/arch/x86/nehalemex/counter.json
new file mode 100644
index 000000000000..ecf0795dceab
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/counter.json
@@ -0,0 +1,7 @@
+[
+ {
+ "Unit": "core",
+ "CountersNumFixed": "4",
+ "CountersNumGeneric": "4"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json b/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
index 196ae1d9b157..9bac9313b65c 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "X87 Floating point assists (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.ALL",
"PEBS": "1",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.INPUT",
"PEBS": "1",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.OUTPUT",
"PEBS": "1",
@@ -25,6 +28,7 @@
},
{
"BriefDescription": "MMX Uops",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
@@ -32,6 +36,7 @@
},
{
"BriefDescription": "SSE2 integer Uops",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
@@ -39,6 +44,7 @@
},
{
"BriefDescription": "SSE* FP double precision Uops",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -46,6 +52,7 @@
},
{
"BriefDescription": "SSE and SSE2 FP Uops",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
@@ -53,6 +60,7 @@
},
{
"BriefDescription": "SSE FP packed Uops",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
@@ -60,6 +68,7 @@
},
{
"BriefDescription": "SSE FP scalar Uops",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
@@ -67,6 +76,7 @@
},
{
"BriefDescription": "SSE* FP single precision Uops",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -74,6 +84,7 @@
},
{
"BriefDescription": "Computational floating-point operations executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
@@ -81,6 +92,7 @@
},
{
"BriefDescription": "All Floating Point to and from MMX transitions",
+ "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
@@ -88,6 +100,7 @@
},
{
"BriefDescription": "Transitions from MMX to Floating Point instructions",
+ "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
@@ -95,6 +108,7 @@
},
{
"BriefDescription": "Transitions from Floating Point to MMX instructions",
+ "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
@@ -102,6 +116,7 @@
},
{
"BriefDescription": "128 bit SIMD integer pack operations",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
@@ -109,6 +124,7 @@
},
{
"BriefDescription": "128 bit SIMD integer arithmetic operations",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -116,6 +132,7 @@
},
{
"BriefDescription": "128 bit SIMD integer logical operations",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -123,6 +140,7 @@
},
{
"BriefDescription": "128 bit SIMD integer multiply operations",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -130,6 +148,7 @@
},
{
"BriefDescription": "128 bit SIMD integer shift operations",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -137,6 +156,7 @@
},
{
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -144,6 +164,7 @@
},
{
"BriefDescription": "128 bit SIMD integer unpack operations",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
@@ -151,6 +172,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit pack operations",
+ "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
@@ -158,6 +180,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
+ "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -165,6 +188,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit logical operations",
+ "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -172,6 +196,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
+ "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -179,6 +204,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit shift operations",
+ "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -186,6 +212,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
+ "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -193,6 +220,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit unpack operations",
+ "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json b/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
index f7f28510e3ae..c561ac24d91d 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Instructions decoded",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Macro-fused instructions decoded",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "Two Uop instructions decoded",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json b/tools/perf/pmu-events/arch/x86/nehalemex/memory.json
index f810880a295e..dc732c8baf12 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Offcore data reads satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -10,6 +11,7 @@
},
{
"BriefDescription": "Offcore data reads that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -19,6 +21,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -28,6 +31,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -37,6 +41,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -46,6 +51,7 @@
},
{
"BriefDescription": "Offcore code reads that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -55,6 +61,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -64,6 +71,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -73,6 +81,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -82,6 +91,7 @@
},
{
"BriefDescription": "Offcore requests that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -91,6 +101,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -100,6 +111,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -109,6 +121,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -118,6 +131,7 @@
},
{
"BriefDescription": "Offcore RFO requests that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -127,6 +141,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -136,6 +151,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -145,6 +161,7 @@
},
{
"BriefDescription": "Offcore writebacks to any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -154,6 +171,7 @@
},
{
"BriefDescription": "Offcore writebacks that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -163,6 +181,7 @@
},
{
"BriefDescription": "Offcore writebacks to the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -172,6 +191,7 @@
},
{
"BriefDescription": "Offcore writebacks to a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -181,6 +201,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -190,6 +211,7 @@
},
{
"BriefDescription": "Offcore code or data read requests that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -199,6 +221,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -208,6 +231,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -217,6 +241,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -226,6 +251,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = any LLC miss",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -235,6 +261,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -244,6 +271,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -253,6 +281,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -262,6 +291,7 @@
},
{
"BriefDescription": "Offcore demand data requests that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -271,6 +301,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -280,6 +311,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -289,6 +321,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -298,6 +331,7 @@
},
{
"BriefDescription": "Offcore demand data reads that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -307,6 +341,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -316,6 +351,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -325,6 +361,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -334,6 +371,7 @@
},
{
"BriefDescription": "Offcore demand code reads that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -343,6 +381,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -352,6 +391,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -361,6 +401,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -370,6 +411,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -379,6 +421,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -388,6 +431,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -397,6 +441,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -406,6 +451,7 @@
},
{
"BriefDescription": "Offcore other requests that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -415,6 +461,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -424,6 +471,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -433,6 +481,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -442,6 +491,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -451,6 +501,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -460,6 +511,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -469,6 +521,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -478,6 +531,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -487,6 +541,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -496,6 +551,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -505,6 +561,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -514,6 +571,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -523,6 +581,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -532,6 +591,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -541,6 +601,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -550,6 +611,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -559,6 +621,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@@ -568,6 +631,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
@@ -577,6 +641,7 @@
},
{
"BriefDescription": "Offcore prefetch requests that missed the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@@ -586,6 +651,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@@ -595,6 +661,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/other.json b/tools/perf/pmu-events/arch/x86/nehalemex/other.json
index fb706cb51832..f6887b234b0e 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/other.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/other.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "ES segment renames",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "I/O transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "L1I instruction fetch stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
@@ -22,6 +25,7 @@
},
{
"BriefDescription": "L1I instruction fetch hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
@@ -29,6 +33,7 @@
},
{
"BriefDescription": "L1I instruction fetch misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
@@ -36,6 +41,7 @@
},
{
"BriefDescription": "L1I Instruction fetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
@@ -43,6 +49,7 @@
},
{
"BriefDescription": "Large ITLB hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
@@ -50,6 +57,7 @@
},
{
"BriefDescription": "All loads dispatched",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
@@ -57,6 +65,7 @@
},
{
"BriefDescription": "Loads dispatched from the MOB",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
@@ -64,6 +73,7 @@
},
{
"BriefDescription": "Loads dispatched that bypass the MOB",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
@@ -71,6 +81,7 @@
},
{
"BriefDescription": "Loads dispatched from stage 305",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
@@ -78,6 +89,7 @@
},
{
"BriefDescription": "False dependencies due to partial address aliasing",
+ "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
@@ -85,6 +97,7 @@
},
{
"BriefDescription": "All Store buffer stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
@@ -92,6 +105,7 @@
},
{
"BriefDescription": "Segment rename stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
@@ -99,6 +113,7 @@
},
{
"BriefDescription": "Thread responded HIT to snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
@@ -106,6 +121,7 @@
},
{
"BriefDescription": "Thread responded HITE to snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
@@ -113,6 +129,7 @@
},
{
"BriefDescription": "Thread responded HITM to snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
@@ -120,6 +137,7 @@
},
{
"BriefDescription": "Super Queue full stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json b/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
index c45f2ffa861e..869c84fa7c60 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Cycles the divider is busy",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Divide Operations executed",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -18,6 +20,7 @@
},
{
"BriefDescription": "Multiply operations executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.MUL",
"SampleAfterValue": "2000000",
@@ -25,6 +28,7 @@
},
{
"BriefDescription": "BACLEAR asserted with bad target address",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.BAD_TARGET",
"SampleAfterValue": "2000000",
@@ -32,6 +36,7 @@
},
{
"BriefDescription": "BACLEAR asserted, regardless of cause",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.CLEAR",
"SampleAfterValue": "2000000",
@@ -39,6 +44,7 @@
},
{
"BriefDescription": "Instruction queue forced BACLEAR",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "BACLEAR_FORCE_IQ",
"SampleAfterValue": "2000000",
@@ -46,6 +52,7 @@
},
{
"BriefDescription": "Early Branch Prediciton Unit clears",
+ "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
@@ -53,6 +60,7 @@
},
{
"BriefDescription": "Late Branch Prediction Unit clears",
+ "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
@@ -60,6 +68,7 @@
},
{
"BriefDescription": "Branch prediction unit missed call or return",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
@@ -67,6 +76,7 @@
},
{
"BriefDescription": "Branch instructions decoded",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
@@ -74,6 +84,7 @@
},
{
"BriefDescription": "Branch instructions executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ANY",
"SampleAfterValue": "200000",
@@ -81,6 +92,7 @@
},
{
"BriefDescription": "Conditional branch instructions executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.COND",
"SampleAfterValue": "200000",
@@ -88,6 +100,7 @@
},
{
"BriefDescription": "Unconditional branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT",
"SampleAfterValue": "200000",
@@ -95,6 +108,7 @@
},
{
"BriefDescription": "Unconditional call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -102,6 +116,7 @@
},
{
"BriefDescription": "Indirect call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -109,6 +124,7 @@
},
{
"BriefDescription": "Indirect non call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "20000",
@@ -116,6 +132,7 @@
},
{
"BriefDescription": "Call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NEAR_CALLS",
"SampleAfterValue": "20000",
@@ -123,6 +140,7 @@
},
{
"BriefDescription": "All non call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NON_CALLS",
"SampleAfterValue": "200000",
@@ -130,6 +148,7 @@
},
{
"BriefDescription": "Indirect return branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.RETURN_NEAR",
"SampleAfterValue": "20000",
@@ -137,6 +156,7 @@
},
{
"BriefDescription": "Taken branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN",
"SampleAfterValue": "200000",
@@ -144,6 +164,7 @@
},
{
"BriefDescription": "Retired branch instructions (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -152,6 +173,7 @@
},
{
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -160,6 +182,7 @@
},
{
"BriefDescription": "Retired near call instructions (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -168,6 +191,7 @@
},
{
"BriefDescription": "Mispredicted branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ANY",
"SampleAfterValue": "20000",
@@ -175,6 +199,7 @@
},
{
"BriefDescription": "Mispredicted conditional branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.COND",
"SampleAfterValue": "20000",
@@ -182,6 +207,7 @@
},
{
"BriefDescription": "Mispredicted unconditional branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT",
"SampleAfterValue": "20000",
@@ -189,6 +215,7 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -196,6 +223,7 @@
},
{
"BriefDescription": "Mispredicted indirect call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -203,6 +231,7 @@
},
{
"BriefDescription": "Mispredicted indirect non call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "2000",
@@ -210,6 +239,7 @@
},
{
"BriefDescription": "Mispredicted call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
"SampleAfterValue": "2000",
@@ -217,6 +247,7 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NON_CALLS",
"SampleAfterValue": "20000",
@@ -224,6 +255,7 @@
},
{
"BriefDescription": "Mispredicted return branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
"SampleAfterValue": "2000",
@@ -231,6 +263,7 @@
},
{
"BriefDescription": "Mispredicted taken branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN",
"SampleAfterValue": "20000",
@@ -238,6 +271,7 @@
},
{
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -246,11 +280,13 @@
},
{
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
+ "Counter": "Fixed counter 3",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_P",
"SampleAfterValue": "100000",
@@ -258,17 +294,20 @@
},
{
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
+ "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Total CPU cycles",
+ "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
@@ -277,6 +316,7 @@
},
{
"BriefDescription": "Any Instruction Length Decoder stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.ANY",
"SampleAfterValue": "2000000",
@@ -284,6 +324,7 @@
},
{
"BriefDescription": "Instruction Queue full stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
@@ -291,6 +332,7 @@
},
{
"BriefDescription": "Length Change Prefix stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000000",
@@ -298,6 +340,7 @@
},
{
"BriefDescription": "Stall cycles due to BPU MRU bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.MRU",
"SampleAfterValue": "2000000",
@@ -305,6 +348,7 @@
},
{
"BriefDescription": "Regen stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.REGEN",
"SampleAfterValue": "2000000",
@@ -312,6 +356,7 @@
},
{
"BriefDescription": "Instructions that must be decoded by decoder 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "INST_DECODED.DEC0",
"SampleAfterValue": "2000000",
@@ -319,6 +364,7 @@
},
{
"BriefDescription": "Instructions written to instruction queue.",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "INST_QUEUE_WRITES",
"SampleAfterValue": "2000000",
@@ -326,6 +372,7 @@
},
{
"BriefDescription": "Cycles instructions are written to the instruction queue",
+ "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "INST_QUEUE_WRITE_CYCLES",
"SampleAfterValue": "2000000",
@@ -333,11 +380,13 @@
},
{
"BriefDescription": "Instructions retired (fixed counter)",
+ "Counter": "Fixed counter 1",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
@@ -346,6 +395,7 @@
},
{
"BriefDescription": "Retired MMX instructions (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.MMX",
"PEBS": "1",
@@ -354,6 +404,7 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
+ "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -364,6 +415,7 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
+ "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -374,6 +426,7 @@
},
{
"BriefDescription": "Retired floating-point operations (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PEBS": "1",
@@ -382,6 +435,7 @@
},
{
"BriefDescription": "Load operations conflicting with software prefetches",
+ "Counter": "0,1",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE",
"SampleAfterValue": "200000",
@@ -389,6 +443,7 @@
},
{
"BriefDescription": "Cycles when uops were delivered by the LSD",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.ACTIVE",
@@ -397,6 +452,7 @@
},
{
"BriefDescription": "Cycles no uops were delivered by the LSD",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.INACTIVE",
@@ -406,6 +462,7 @@
},
{
"BriefDescription": "Loops that can't stream from the instruction queue",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "LSD_OVERFLOW",
"SampleAfterValue": "2000000",
@@ -413,6 +470,7 @@
},
{
"BriefDescription": "Cycles machine clear asserted",
+ "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "20000",
@@ -420,6 +478,7 @@
},
{
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
+ "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEM_ORDER",
"SampleAfterValue": "20000",
@@ -427,6 +486,7 @@
},
{
"BriefDescription": "Self-Modifying Code detected",
+ "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20000",
@@ -434,6 +494,7 @@
},
{
"BriefDescription": "All RAT stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -441,6 +502,7 @@
},
{
"BriefDescription": "Flag stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
@@ -448,6 +510,7 @@
},
{
"BriefDescription": "Partial register stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
@@ -455,6 +518,7 @@
},
{
"BriefDescription": "ROB read port stalls cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
@@ -462,6 +526,7 @@
},
{
"BriefDescription": "Scoreboard stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
@@ -469,6 +534,7 @@
},
{
"BriefDescription": "Resource related stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -476,6 +542,7 @@
},
{
"BriefDescription": "FPU control word write stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.FPCW",
"SampleAfterValue": "2000000",
@@ -483,6 +550,7 @@
},
{
"BriefDescription": "Load buffer stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LOAD",
"SampleAfterValue": "2000000",
@@ -490,6 +558,7 @@
},
{
"BriefDescription": "MXCSR rename stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MXCSR",
"SampleAfterValue": "2000000",
@@ -497,6 +566,7 @@
},
{
"BriefDescription": "Other Resource related stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OTHER",
"SampleAfterValue": "2000000",
@@ -504,6 +574,7 @@
},
{
"BriefDescription": "ROB full stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB_FULL",
"SampleAfterValue": "2000000",
@@ -511,6 +582,7 @@
},
{
"BriefDescription": "Reservation Station full stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS_FULL",
"SampleAfterValue": "2000000",
@@ -518,6 +590,7 @@
},
{
"BriefDescription": "Store buffer stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.STORE",
"SampleAfterValue": "2000000",
@@ -525,6 +598,7 @@
},
{
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
"PEBS": "1",
@@ -533,6 +607,7 @@
},
{
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
"PEBS": "1",
@@ -541,6 +616,7 @@
},
{
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
"PEBS": "1",
@@ -549,6 +625,7 @@
},
{
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
"PEBS": "1",
@@ -557,6 +634,7 @@
},
{
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
"PEBS": "1",
@@ -565,6 +643,7 @@
},
{
"BriefDescription": "Stack pointer instructions decoded",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_FOLDING",
"SampleAfterValue": "2000000",
@@ -572,6 +651,7 @@
},
{
"BriefDescription": "Stack pointer sync operations",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_SYNC",
"SampleAfterValue": "2000000",
@@ -579,6 +659,7 @@
},
{
"BriefDescription": "Uops decoded by Microcode Sequencer",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -587,6 +668,7 @@
},
{
"BriefDescription": "Cycles no Uops are decoded",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -597,6 +679,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on any port (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -606,6 +689,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -615,6 +699,7 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on any port (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -626,6 +711,7 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on ports 0-4 (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -637,6 +723,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on any port (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -647,6 +734,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -656,6 +744,7 @@
},
{
"BriefDescription": "Uops executed on port 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT0",
"SampleAfterValue": "2000000",
@@ -663,6 +752,7 @@
},
{
"BriefDescription": "Uops issued on ports 0, 1 or 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015",
"SampleAfterValue": "2000000",
@@ -670,6 +760,7 @@
},
{
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -679,6 +770,7 @@
},
{
"BriefDescription": "Uops executed on port 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT1",
"SampleAfterValue": "2000000",
@@ -687,6 +779,7 @@
{
"AnyThread": "1",
"BriefDescription": "Uops issued on ports 2, 3 or 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT234_CORE",
"SampleAfterValue": "2000000",
@@ -695,6 +788,7 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 2 (core count)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT2_CORE",
"SampleAfterValue": "2000000",
@@ -703,6 +797,7 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 3 (core count)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT3_CORE",
"SampleAfterValue": "2000000",
@@ -711,6 +806,7 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 4 (core count)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT4_CORE",
"SampleAfterValue": "2000000",
@@ -718,6 +814,7 @@
},
{
"BriefDescription": "Uops executed on port 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT5",
"SampleAfterValue": "2000000",
@@ -725,6 +822,7 @@
},
{
"BriefDescription": "Uops issued",
+ "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "2000000",
@@ -733,6 +831,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops were issued on any thread",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -743,6 +842,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops were issued on either thread",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -751,6 +851,7 @@
},
{
"BriefDescription": "Fused Uops issued",
+ "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.FUSED",
"SampleAfterValue": "2000000",
@@ -758,6 +859,7 @@
},
{
"BriefDescription": "Cycles no Uops were issued",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -767,6 +869,7 @@
},
{
"BriefDescription": "Cycles Uops are being retired",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -776,6 +879,7 @@
},
{
"BriefDescription": "Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"PEBS": "1",
@@ -784,6 +888,7 @@
},
{
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PEBS": "1",
@@ -792,6 +897,7 @@
},
{
"BriefDescription": "Retirement slots used (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -800,6 +906,7 @@
},
{
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -810,6 +917,7 @@
},
{
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
+ "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -820,6 +928,7 @@
},
{
"BriefDescription": "Uop unfusions due to FP exceptions",
+ "Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UOP_UNFUSION",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
index c434cd4ef4f1..e88c0802e679 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "DTLB load misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "DTLB load miss caused by low part of address",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "DTLB second level hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
@@ -22,6 +25,7 @@
},
{
"BriefDescription": "DTLB load miss page walks complete",
+ "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -29,6 +33,7 @@
},
{
"BriefDescription": "DTLB misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -36,6 +41,7 @@
},
{
"BriefDescription": "DTLB first level misses but second level hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
@@ -43,6 +49,7 @@
},
{
"BriefDescription": "DTLB miss page walks",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -50,6 +57,7 @@
},
{
"BriefDescription": "ITLB flushes",
+ "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
@@ -57,6 +65,7 @@
},
{
"BriefDescription": "ITLB miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -64,6 +73,7 @@
},
{
"BriefDescription": "ITLB miss page walks",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -71,6 +81,7 @@
},
{
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC8",
"EventName": "ITLB_MISS_RETIRED",
"PEBS": "1",
@@ -79,6 +90,7 @@
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
@@ -87,6 +99,7 @@
},
{
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"PEBS": "1",
--
2.45.2.627.g7a2c4fd464-goog
Powered by blists - more mailing lists