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Message-Id: <20240620181752.3945845-18-irogers@google.com>
Date: Thu, 20 Jun 2024 11:17:31 -0700
From: Ian Rogers <irogers@...gle.com>
To: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>, Jiri Olsa <jolsa@...nel.org>,
Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>,
Kan Liang <kan.liang@...ux.intel.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org
Cc: Weilin Wang <weilin.wang@...el.com>, Caleb Biggers <caleb.biggers@...el.com>
Subject: [PATCH v2 17/37] perf vendor events: Add/update icelakex events/metrics
Update events from v1.24 to v1.26.
Add TMA metrics v4.8.
Bring in the event updates v1.26:
https://github.com/intel/perfmon/commit/c607c739e05f2569f95998cc98e1283f042b4fd1
v1.25:
https://github.com/intel/perfmon/commit/42d996769069921ec06f6fbb600b0c663b9ec5a9
The TMA 4.8 information was added in:
https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9a5736
Adds the event SW_PREFETCH_ACCESS.ANY.
Co-authored-by: Weilin Wang <weilin.wang@...el.com>
Co-authored-by: Caleb Biggers <caleb.biggers@...el.com>
Signed-off-by: Ian Rogers <irogers@...gle.com>
Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>
---
.../pmu-events/arch/x86/icelakex/cache.json | 106 +
.../pmu-events/arch/x86/icelakex/counter.json | 57 +
.../arch/x86/icelakex/floating-point.json | 13 +
.../arch/x86/icelakex/frontend.json | 38 +
.../arch/x86/icelakex/icx-metrics.json | 340 +-
.../pmu-events/arch/x86/icelakex/memory.json | 45 +
.../arch/x86/icelakex/metricgroups.json | 13 +
.../pmu-events/arch/x86/icelakex/other.json | 52 +
.../arch/x86/icelakex/pipeline.json | 92 +
.../arch/x86/icelakex/uncore-cache.json | 2149 ++++++++++-
.../x86/icelakex/uncore-interconnect.json | 3344 +++++++++++++++++
.../arch/x86/icelakex/uncore-io.json | 1829 +++++++++
.../arch/x86/icelakex/uncore-memory.json | 338 ++
.../arch/x86/icelakex/uncore-power.json | 51 +
.../arch/x86/icelakex/virtual-memory.json | 22 +
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
16 files changed, 8269 insertions(+), 222 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/counter.json
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
index 3bdc56a75097..0cbb9d6a3ec1 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x48",
@@ -27,6 +30,7 @@
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALL",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
@@ -35,6 +39,7 @@
},
{
"BriefDescription": "Number of L1D misses that are outstanding",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -43,6 +48,7 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -52,6 +58,7 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -60,6 +67,7 @@
},
{
"BriefDescription": "Cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.NON_SILENT",
"PublicDescription": "Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities.",
@@ -68,6 +76,7 @@
},
{
"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.SILENT",
"PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
@@ -76,6 +85,7 @@
},
{
"BriefDescription": "L2 code requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts the total number of L2 code requests.",
@@ -84,6 +94,7 @@
},
{
"BriefDescription": "Demand Data Read requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -92,6 +103,7 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"PublicDescription": "Counts demand requests that miss L2 cache.",
@@ -100,6 +112,7 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -108,6 +121,7 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
@@ -116,6 +130,7 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
@@ -124,6 +139,7 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
@@ -132,6 +148,7 @@
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -140,6 +157,7 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
@@ -148,6 +166,7 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
@@ -156,6 +175,7 @@
},
{
"BriefDescription": "SW prefetch requests that hit L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
@@ -164,6 +184,7 @@
},
{
"BriefDescription": "SW prefetch requests that miss L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
@@ -172,6 +193,7 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "Counts L2 writebacks that access L2 cache.",
@@ -180,6 +202,7 @@
},
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
@@ -188,6 +211,7 @@
},
{
"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
@@ -196,6 +220,7 @@
},
{
"BriefDescription": "Retired load instructions.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
@@ -206,6 +231,7 @@
},
{
"BriefDescription": "Retired store instructions.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
@@ -216,6 +242,7 @@
},
{
"BriefDescription": "All retired memory instructions.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ANY",
@@ -226,6 +253,7 @@
},
{
"BriefDescription": "Retired load instructions with locked access.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
@@ -236,6 +264,7 @@
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
@@ -246,6 +275,7 @@
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
@@ -256,6 +286,7 @@
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
@@ -266,6 +297,7 @@
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
@@ -276,6 +308,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
@@ -286,6 +319,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"Deprecated": "1",
"EventCode": "0xd2",
@@ -296,6 +330,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"Deprecated": "1",
"EventCode": "0xd2",
@@ -306,6 +341,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -316,6 +352,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
@@ -326,6 +363,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@@ -336,6 +374,7 @@
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
@@ -346,6 +385,7 @@
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
@@ -355,6 +395,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
@@ -365,6 +406,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources was remote HITM",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
@@ -375,6 +417,7 @@
},
{
"BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
@@ -385,6 +428,7 @@
},
{
"BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
@@ -395,6 +439,7 @@
},
{
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
@@ -405,6 +450,7 @@
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
@@ -415,6 +461,7 @@
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
@@ -425,6 +472,7 @@
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
@@ -435,6 +483,7 @@
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
@@ -445,6 +494,7 @@
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
@@ -455,6 +505,7 @@
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
@@ -465,6 +516,7 @@
},
{
"BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.LOCAL_PMM",
@@ -475,6 +527,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -484,6 +537,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -493,6 +547,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -502,6 +557,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -511,6 +567,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -520,6 +577,7 @@
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -529,6 +587,7 @@
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -538,6 +597,7 @@
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -547,6 +607,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -556,6 +617,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -565,6 +627,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -574,6 +637,7 @@
},
{
"BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -583,6 +647,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -592,6 +657,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -601,6 +667,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -610,6 +677,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -619,6 +687,7 @@
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -628,6 +697,7 @@
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -637,6 +707,7 @@
},
{
"BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PREFETCHES.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -646,6 +717,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -655,6 +727,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -664,6 +737,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -673,6 +747,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -682,6 +757,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -691,6 +767,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -700,6 +777,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -709,6 +787,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -718,6 +797,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -727,6 +807,7 @@
},
{
"BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -736,6 +817,7 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -744,6 +826,7 @@
},
{
"BriefDescription": "Counts memory transactions sent to the uncore.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.",
@@ -752,6 +835,7 @@
},
{
"BriefDescription": "Counts cacheable and non-cacheable code reads to the core.",
+ "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Counts both cacheable and non-cacheable code reads to the core.",
@@ -760,6 +844,7 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
+ "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -768,6 +853,7 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
+ "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -776,6 +862,7 @@
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
@@ -784,6 +871,7 @@
},
{
"BriefDescription": "Cycles where at least 1 outstanding data read request is pending.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -793,6 +881,7 @@
},
{
"BriefDescription": "Cycles with outstanding code read requests pending.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -802,6 +891,7 @@
},
{
"BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -811,6 +901,7 @@
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding code read requests pending.",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "For every cycle, increments by the number of outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
@@ -819,6 +910,7 @@
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
@@ -827,6 +919,7 @@
},
{
"BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
+ "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.BUS_LOCK",
"PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",
@@ -835,14 +928,24 @@
},
{
"BriefDescription": "Cycles the queue waiting for offcore responses is full.",
+ "Counter": "0,1,2,3",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SQ_FULL",
"PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
+ {
+ "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.ANY",
+ "SampleAfterValue": "100003",
+ "UMask": "0xf"
+ },
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.NTA",
"PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
@@ -851,6 +954,7 @@
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"PublicDescription": "Counts the number of PREFETCHW instructions executed.",
@@ -859,6 +963,7 @@
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T0",
"PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
@@ -867,6 +972,7 @@
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
"PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/counter.json b/tools/perf/pmu-events/arch/x86/icelakex/counter.json
new file mode 100644
index 000000000000..63657e0a51a3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/icelakex/counter.json
@@ -0,0 +1,57 @@
+[
+ {
+ "Unit": "core",
+ "CountersNumFixed": "4",
+ "CountersNumGeneric": "8"
+ },
+ {
+ "Unit": "CHA",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "IIO",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "IRP",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "2"
+ },
+ {
+ "Unit": "iMC",
+ "CountersNumFixed": "1",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "M2M",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "UPI",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "M2PCIe",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "M3UPI",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "PCU",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "UBOX",
+ "CountersNumFixed": 1,
+ "CountersNumGeneric": "2"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
index 85c26c889088..61ddce0c8db6 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts all microcode FP assists.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.FP",
"PublicDescription": "Counts all microcode Floating Point assists.",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -25,6 +28,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -33,6 +37,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -41,6 +46,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -49,6 +55,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -57,6 +64,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -65,6 +73,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.8_FLOPS",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -73,6 +82,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -81,6 +91,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -89,6 +100,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -97,6 +109,7 @@
},
{
"BriefDescription": "Number of any Vector retired FP arithmetic instructions",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.VECTOR",
"SampleAfterValue": "1000003",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
index 66669d062e68..d79ddc15b220 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
+ "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "DECODE.LCP",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xab",
@@ -27,6 +30,7 @@
},
{
"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
+ "Counter": "0,1,2,3",
"EventCode": "0xab",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
@@ -35,6 +39,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
@@ -46,6 +51,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
@@ -57,6 +63,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
@@ -68,6 +75,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
@@ -79,6 +87,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
@@ -90,6 +99,7 @@
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
@@ -101,6 +111,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
@@ -112,6 +123,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
@@ -123,6 +135,7 @@
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
@@ -134,6 +147,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
@@ -145,6 +159,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
@@ -156,6 +171,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
@@ -167,6 +183,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
@@ -178,6 +195,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
@@ -189,6 +207,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
@@ -200,6 +219,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
@@ -211,6 +231,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
@@ -222,6 +243,7 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]",
@@ -230,6 +252,7 @@
},
{
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT",
"PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
@@ -238,6 +261,7 @@
},
{
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS",
"PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
@@ -246,6 +270,7 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_STALL",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
@@ -254,6 +279,7 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE_DATA.STALLS",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]",
@@ -262,6 +288,7 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_TAG.STALLS",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
@@ -270,6 +297,7 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY",
@@ -279,6 +307,7 @@
},
{
"BriefDescription": "Cycles DSB is delivering optimal number of Uops",
+ "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
@@ -288,6 +317,7 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
@@ -296,6 +326,7 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_ANY",
@@ -305,6 +336,7 @@
},
{
"BriefDescription": "Cycles MITE is delivering optimal number of Uops",
+ "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_OK",
@@ -314,6 +346,7 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -322,6 +355,7 @@
},
{
"BriefDescription": "Number of switches from DSB or MITE to the MS",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -332,6 +366,7 @@
},
{
"BriefDescription": "Uops delivered to IDQ while MS is busy",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
@@ -340,6 +375,7 @@
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
@@ -348,6 +384,7 @@
},
{
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -357,6 +394,7 @@
},
{
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
index 769ba12bef87..db5510ba9099 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
@@ -47,7 +47,7 @@
},
{
"BriefDescription": "Percentage of time spent in the active CPU power state C0",
- "MetricExpr": "tma_info_system_cpu_utilization",
+ "MetricExpr": "tma_info_system_cpus_utilized",
"MetricName": "cpu_utilization",
"ScaleUnit": "100%"
},
@@ -72,12 +72,36 @@
"PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
"ScaleUnit": "1per_instr"
},
+ {
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_read_local",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_read_remote",
+ "ScaleUnit": "1MB/s"
+ },
{
"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
"MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time",
"MetricName": "io_bandwidth_write",
"ScaleUnit": "1MB/s"
},
+ {
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_write_local",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_write_remote",
+ "ScaleUnit": "1MB/s"
+ },
{
"BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
"MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
@@ -308,7 +332,7 @@
{
"BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
"MetricExpr": "34 * ASSISTS.ANY / tma_info_thread_slots",
- "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
"MetricName": "tma_assists",
"MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)",
"PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY",
@@ -318,7 +342,7 @@
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
"DefaultMetricgroupName": "TopdownL1",
"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / tma_info_thread_slots",
- "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group",
+ "MetricGroup": "BvOB;Default;TmaL1;TopdownL1;tma_L1_group",
"MetricName": "tma_backend_bound",
"MetricThreshold": "tma_backend_bound > 0.2",
"MetricgroupNoGroup": "TopdownL1;Default",
@@ -339,7 +363,7 @@
{
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.",
"MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * tma_info_thread_slots)",
- "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
"MetricName": "tma_branch_instructions",
"MetricThreshold": "tma_branch_instructions > 0.1 & tma_light_operations > 0.6",
"ScaleUnit": "100%"
@@ -347,7 +371,7 @@
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
- "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
+ "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
"MetricName": "tma_branch_mispredicts",
"MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15",
"MetricgroupNoGroup": "TopdownL2",
@@ -385,7 +409,7 @@
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
"MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "(44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 43.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
+ "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache",
@@ -405,7 +429,7 @@
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
"MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "43.5 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
- "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
+ "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache",
@@ -423,7 +447,7 @@
{
"BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
"MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks",
- "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group",
"MetricName": "tma_divider",
"MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
"PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
@@ -454,13 +478,13 @@
"MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB",
"MetricName": "tma_dsb_switches",
"MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
"ScaleUnit": "100%"
},
{
"BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
"MetricExpr": "min(7 * cpu@...B_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group",
+ "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group",
"MetricName": "tma_dtlb_load",
"MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization",
@@ -469,7 +493,7 @@
{
"BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
"MetricExpr": "(7 * cpu@...B_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group",
+ "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group",
"MetricName": "tma_dtlb_store",
"MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization",
@@ -478,7 +502,7 @@
{
"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
"MetricExpr": "48 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group",
+ "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group",
"MetricName": "tma_false_sharing",
"MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache",
@@ -487,7 +511,7 @@
{
"BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
"MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_thread_clks",
- "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group",
+ "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group",
"MetricName": "tma_fb_full",
"MetricThreshold": "tma_fb_full > 0.3",
"PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores",
@@ -500,7 +524,7 @@
"MetricName": "tma_fetch_bandwidth",
"MetricThreshold": "tma_fetch_bandwidth > 0.2",
"MetricgroupNoGroup": "TopdownL2",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
"ScaleUnit": "100%"
},
{
@@ -542,7 +566,7 @@
},
{
"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
- "MetricExpr": "cpu@...ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / (tma_retiring * tma_info_thread_slots)",
+ "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / (tma_retiring * tma_info_thread_slots)",
"MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P",
"MetricName": "tma_fp_scalar",
"MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)",
@@ -551,7 +575,7 @@
},
{
"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
- "MetricExpr": "cpu@...ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ / (tma_retiring * tma_info_thread_slots)",
+ "MetricExpr": "FP_ARITH_INST_RETIRED.VECTOR / (tma_retiring * tma_info_thread_slots)",
"MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P",
"MetricName": "tma_fp_vector",
"MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)",
@@ -589,7 +613,7 @@
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
"DefaultMetricgroupName": "TopdownL1",
"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_thread_slots",
- "MetricGroup": "Default;PGO;TmaL1;TopdownL1;tma_L1_group",
+ "MetricGroup": "BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group",
"MetricName": "tma_frontend_bound",
"MetricThreshold": "tma_frontend_bound > 0.15",
"MetricgroupNoGroup": "TopdownL1;Default",
@@ -609,7 +633,7 @@
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
"MetricExpr": "ICACHE_DATA.STALLS / tma_info_thread_clks",
- "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
"MetricName": "tma_icache_misses",
"MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
@@ -664,24 +688,6 @@
"MetricGroup": "BrMispredicts",
"MetricName": "tma_info_bad_spec_spec_clears_ratio"
},
- {
- "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
- "MetricExpr": "(100 * (1 - max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) / (((cpu@..._ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) < (((cpu@..._ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0)",
- "MetricGroup": "Cor;SMT",
- "MetricName": "tma_info_botlnk_core_bound_likely"
- },
- {
- "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
- "MetricExpr": "100 * (100 * ((5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) + max(0, topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots - (5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots) * ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2) / ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2 + (IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2)))",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "tma_info_botlnk_dsb_misses"
- },
- {
- "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.",
- "MetricExpr": "100 * (100 * ((5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots * (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD)))",
- "MetricGroup": "Fed;FetchLat;IcMiss",
- "MetricName": "tma_info_botlnk_ic_misses"
- },
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
"MetricConstraint": "NO_GROUP_EVENTS",
@@ -690,6 +696,14 @@
"MetricName": "tma_info_botlnk_l0_core_bound_likely",
"MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5"
},
+ {
+ "BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck",
+ "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite)))",
+ "MetricGroup": "DSB;FetchBW;tma_issueFB",
+ "MetricName": "tma_info_botlnk_l2_dsb_bandwidth",
+ "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10",
+ "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp"
+ },
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck",
"MetricConstraint": "NO_GROUP_EVENTS",
@@ -697,7 +711,7 @@
"MetricGroup": "DSBmiss;Fed;tma_issueFB",
"MetricName": "tma_info_botlnk_l2_dsb_misses",
"MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10",
- "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp"
+ "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp"
},
{
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck",
@@ -708,40 +722,34 @@
"MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5",
"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: "
},
- {
- "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.",
- "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
- "MetricGroup": "Ret",
- "MetricName": "tma_info_bottleneck_base_non_br",
- "MetricThreshold": "tma_info_bottleneck_base_non_br > 20"
- },
{
"BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
"MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
- "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB",
+ "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB",
"MetricName": "tma_info_bottleneck_big_code",
"MetricThreshold": "tma_info_bottleneck_big_code > 20"
},
{
- "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
- "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots)",
- "MetricGroup": "Ret",
+ "BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA",
+ "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)",
+ "MetricGroup": "BvBO;Ret",
"MetricName": "tma_info_bottleneck_branching_overhead",
- "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5"
+ "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5",
+ "PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)"
},
{
"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks",
- "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))",
- "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW",
+ "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))",
+ "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW",
"MetricName": "tma_info_bottleneck_cache_memory_bandwidth",
"MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 20",
"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full"
},
{
"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
- "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
- "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat",
+ "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))",
+ "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat",
"MetricName": "tma_info_bottleneck_cache_memory_latency",
"MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20",
"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency"
@@ -749,23 +757,23 @@
{
"BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
"MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))",
- "MetricGroup": "Cor;tma_issueComp",
+ "MetricGroup": "BvCB;Cor;tma_issueComp",
"MetricName": "tma_info_bottleneck_compute_bound_est",
"MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20",
"PublicDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics: "
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
+ "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)",
"MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code",
- "MetricGroup": "Fed;FetchBW;Frontend",
+ "MetricGroup": "BvFB;Fed;FetchBW;Frontend",
"MetricName": "tma_info_bottleneck_instruction_fetch_bw",
"MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20"
},
{
"BriefDescription": "Total pipeline cost of irregular execution (e.g",
"MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
- "MetricGroup": "Bad;Cor;Ret;tma_issueMS",
+ "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS",
"MetricName": "tma_info_bottleneck_irregular_overhead",
"MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10",
"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches"
@@ -773,8 +781,8 @@
{
"BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
"MetricConstraint": "NO_GROUP_EVENTS",
- "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
- "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB",
+ "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
+ "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB",
"MetricName": "tma_info_bottleneck_memory_data_tlbs",
"MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20",
"PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization"
@@ -782,7 +790,7 @@
{
"BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)",
"MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes))",
- "MetricGroup": "Mem;Offcore;tma_issueTLB",
+ "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB",
"MetricName": "tma_info_bottleneck_memory_synchronization",
"MetricThreshold": "tma_info_bottleneck_memory_synchronization > 10",
"PublicDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs"
@@ -791,18 +799,25 @@
"BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
"MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
- "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM",
"MetricName": "tma_info_bottleneck_mispredictions",
"MetricThreshold": "tma_info_bottleneck_mispredictions > 20",
"PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers"
},
{
- "BriefDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class)",
- "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info_bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_latency + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_synchronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_irregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottleneck_base_non_br)",
- "MetricGroup": "Cor;Offcore",
+ "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
+ "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info_bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_latency + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_synchronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_irregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottleneck_useful_work)",
+ "MetricGroup": "BvOB;Cor;Offcore",
"MetricName": "tma_info_bottleneck_other_bottlenecks",
"MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20",
- "PublicDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class). Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls."
+ "PublicDescription": "Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls."
+ },
+ {
+ "BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.",
+ "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
+ "MetricGroup": "BvUW;Ret",
+ "MetricName": "tma_info_bottleneck_useful_work",
+ "MetricThreshold": "tma_info_bottleneck_useful_work > 20"
},
{
"BriefDescription": "Fraction of branches that are CALL or RET",
@@ -860,7 +875,7 @@
},
{
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "(cpu@...ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@...ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@) / (2 * tma_info_core_core_clks)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED.VECTOR) / (2 * tma_info_core_core_clks)",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "tma_info_core_fp_arith_utilization",
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
@@ -877,7 +892,7 @@
"MetricGroup": "DSB;Fed;FetchBW;tma_issueFB",
"MetricName": "tma_info_frontend_dsb_coverage",
"MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 5 > 0.35",
- "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp"
+ "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp"
},
{
"BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
@@ -937,7 +952,7 @@
},
{
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (cpu@...ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@...ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED.VECTOR)",
"MetricGroup": "Flops;InsType",
"MetricName": "tma_info_inst_mix_iparith",
"MetricThreshold": "tma_info_inst_mix_iparith < 10",
@@ -1032,24 +1047,12 @@
"MetricThreshold": "tma_info_inst_mix_ipswpf < 100"
},
{
- "BriefDescription": "Instruction per taken branch",
+ "BriefDescription": "Instructions per taken branch",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB",
"MetricName": "tma_info_inst_mix_iptb",
"MetricThreshold": "tma_info_inst_mix_iptb < 11",
- "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp"
- },
- {
- "BriefDescription": "\"Bus lock\" per kilo instruction",
- "MetricExpr": "tma_info_memory_mix_bus_lock_pki",
- "MetricGroup": "Mem",
- "MetricName": "tma_info_memory_bus_lock_pki"
- },
- {
- "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
- "MetricExpr": "tma_info_memory_tlb_code_stlb_mpki",
- "MetricGroup": "Fed;MemoryTLB",
- "MetricName": "tma_info_memory_code_stlb_mpki"
+ "PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
@@ -1087,12 +1090,6 @@
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t"
},
- {
- "BriefDescription": "Average Parallel L2 cache miss data reads",
- "MetricExpr": "tma_info_memory_latency_data_l2_mlp",
- "MetricGroup": "Memory_BW;Offcore",
- "MetricName": "tma_info_memory_data_l2_mlp"
- },
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
"MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
@@ -1100,17 +1097,11 @@
"MetricName": "tma_info_memory_fb_hpki"
},
{
- "BriefDescription": "",
+ "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l1d_cache_fill_bw"
},
- {
- "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
- },
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
@@ -1124,29 +1115,11 @@
"MetricName": "tma_info_memory_l1mpki_load"
},
{
- "BriefDescription": "",
+ "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l2_cache_fill_bw"
},
- {
- "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
- },
- {
- "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
- "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki"
- },
- {
- "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
- "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "tma_info_memory_l2_evictions_silent_pki"
- },
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
@@ -1172,29 +1145,23 @@
"MetricName": "tma_info_memory_l2mpki_load"
},
{
- "BriefDescription": "",
- "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "tma_info_memory_l3_cache_access_bw"
+ "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
+ "MetricExpr": "1e3 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Offcore",
+ "MetricName": "tma_info_memory_l2mpki_rfo"
},
{
- "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duration_time * 1e3 / 1e3)",
+ "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "tma_info_memory_l3_cache_access_bw_2t"
+ "MetricName": "tma_info_memory_l3_cache_access_bw"
},
{
- "BriefDescription": "",
+ "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l3_cache_fill_bw"
},
- {
- "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
- },
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
@@ -1209,7 +1176,7 @@
},
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
- "MetricExpr": "tma_info_memory_load_l2_miss_latency",
+ "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
"MetricGroup": "Memory_Lat;Offcore",
"MetricName": "tma_info_memory_latency_load_l2_miss_latency"
},
@@ -1219,29 +1186,11 @@
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_latency_load_l2_mlp"
},
- {
- "BriefDescription": "Average Latency for L3 cache miss demand Loads",
- "MetricExpr": "tma_info_memory_load_l3_miss_latency",
- "MetricGroup": "Memory_Lat;Offcore",
- "MetricName": "tma_info_memory_latency_load_l3_miss_latency"
- },
- {
- "BriefDescription": "Average Latency for L2 cache miss demand Loads",
- "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "MetricGroup": "Memory_Lat;Offcore",
- "MetricName": "tma_info_memory_load_l2_miss_latency"
- },
- {
- "BriefDescription": "Average Parallel L2 cache miss demand Loads",
- "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@...CORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=0x1@",
- "MetricGroup": "Memory_BW;Offcore",
- "MetricName": "tma_info_memory_load_l2_mlp"
- },
{
"BriefDescription": "Average Latency for L3 cache miss demand Loads",
"MetricExpr": "cpu@...CORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,umask\\=0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"MetricGroup": "Memory_Lat;Offcore",
- "MetricName": "tma_info_memory_load_l3_miss_latency"
+ "MetricName": "tma_info_memory_latency_load_l3_miss_latency"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@@ -1249,12 +1198,6 @@
"MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "tma_info_memory_load_miss_real_latency"
},
- {
- "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
- "MetricExpr": "tma_info_memory_tlb_load_stlb_mpki",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "tma_info_memory_load_stlb_mpki"
- },
{
"BriefDescription": "\"Bus lock\" per kilo instruction",
"MetricExpr": "1e3 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY",
@@ -1263,7 +1206,7 @@
},
{
"BriefDescription": "Un-cacheable retired load per kilo instruction",
- "MetricExpr": "tma_info_memory_uc_load_pki",
+ "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
"MetricGroup": "Mem",
"MetricName": "tma_info_memory_mix_uc_load_pki"
},
@@ -1274,18 +1217,6 @@
"MetricName": "tma_info_memory_mlp",
"PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)"
},
- {
- "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
- "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD))",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "tma_info_memory_page_walks_utilization"
- },
- {
- "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
- "MetricExpr": "tma_info_memory_tlb_store_stlb_mpki",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "tma_info_memory_store_stlb_mpki"
- },
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
@@ -1312,17 +1243,23 @@
"MetricName": "tma_info_memory_tlb_store_stlb_mpki"
},
{
- "BriefDescription": "Un-cacheable retired load per kilo instruction",
- "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
- "MetricGroup": "Mem",
- "MetricName": "tma_info_memory_uc_load_pki"
- },
- {
- "BriefDescription": "",
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per core",
"MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else cpu@...S_EXECUTED.THREAD\\,cmask\\=1@)",
"MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
"MetricName": "tma_info_pipeline_execute"
},
+ {
+ "BriefDescription": "Average number of uops fetched from DSB per cycle",
+ "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY",
+ "MetricGroup": "Fed;FetchBW",
+ "MetricName": "tma_info_pipeline_fetch_dsb"
+ },
+ {
+ "BriefDescription": "Average number of uops fetched from MITE per cycle",
+ "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY",
+ "MetricGroup": "Fed;FetchBW",
+ "MetricName": "tma_info_pipeline_fetch_mite"
+ },
{
"BriefDescription": "Instructions per a microcode Assist invocation",
"MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY",
@@ -1345,13 +1282,13 @@
},
{
"BriefDescription": "Average CPU Utilization (percentage)",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online",
"MetricGroup": "HPC;Summary",
"MetricName": "tma_info_system_cpu_utilization"
},
{
"BriefDescription": "Average number of utilized CPUs",
- "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "Summary",
"MetricName": "tma_info_system_cpus_utilized"
},
@@ -1535,7 +1472,7 @@
"MetricThreshold": "tma_info_thread_uoppi > 1.05"
},
{
- "BriefDescription": "Instruction per taken branch",
+ "BriefDescription": "Uops per taken branch",
"MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW",
"MetricName": "tma_info_thread_uptb",
@@ -1544,7 +1481,7 @@
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
"MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks",
- "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
"MetricName": "tma_itlb_misses",
"MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
@@ -1559,11 +1496,20 @@
"PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1",
"ScaleUnit": "100%"
},
+ {
+ "BriefDescription": "This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache",
+ "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks",
+ "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_l1_hit_latency",
+ "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT",
+ "ScaleUnit": "100%"
+ },
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
"MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks)",
- "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
"MetricName": "tma_l2_bound",
"MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)",
"PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
@@ -1582,7 +1528,7 @@
{
"BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
"MetricExpr": "19 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks",
- "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group",
+ "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency",
@@ -1594,7 +1540,7 @@
"MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB",
"MetricName": "tma_lcp",
"MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
- "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb",
+ "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb",
"ScaleUnit": "100%"
},
{
@@ -1638,7 +1584,7 @@
"MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
"MetricName": "tma_local_mem",
"MetricThreshold": "tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
"ScaleUnit": "100%"
},
{
@@ -1648,13 +1594,13 @@
"MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
- "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency",
+ "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
"MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
- "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn",
+ "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn",
"MetricName": "tma_machine_clears",
"MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15",
"MetricgroupNoGroup": "TopdownL2",
@@ -1664,7 +1610,7 @@
{
"BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM)",
"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@...CORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_thread_clks",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW",
+ "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW",
"MetricName": "tma_mem_bandwidth",
"MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full",
@@ -1673,7 +1619,7 @@
{
"BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM)",
"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat",
+ "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat",
"MetricName": "tma_mem_latency",
"MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_latency",
@@ -1710,7 +1656,7 @@
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM",
+ "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM",
"MetricName": "tma_mispredicts_resteers",
"MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions",
@@ -1754,7 +1700,7 @@
{
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
"MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_thread_slots)",
- "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group",
+ "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group",
"MetricName": "tma_nop_instructions",
"MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6)",
"PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
@@ -1773,7 +1719,7 @@
{
"BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).",
"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)",
- "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group",
+ "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_branch_mispredicts_group",
"MetricName": "tma_other_mispredicts",
"MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15)",
"ScaleUnit": "100%"
@@ -1781,7 +1727,7 @@
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.",
"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT), 0.0001)",
- "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group",
+ "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group",
"MetricName": "tma_other_nukes",
"MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15)",
"ScaleUnit": "100%"
@@ -1842,7 +1788,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@..._ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / tma_info_thread_clks * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks",
+ "MetricExpr": "cpu@..._ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / tma_info_thread_clks",
"MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_0",
"MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
@@ -1870,7 +1816,7 @@
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks",
- "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_3m",
"MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
@@ -1898,7 +1844,7 @@
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
"DefaultMetricgroupName": "TopdownL1",
"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_thread_slots",
- "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group",
+ "MetricGroup": "BvUW;Default;TmaL1;TopdownL1;tma_L1_group",
"MetricName": "tma_retiring",
"MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1",
"MetricgroupNoGroup": "TopdownL1;Default",
@@ -1908,7 +1854,7 @@
{
"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
"MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks",
- "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO",
+ "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO",
"MetricName": "tma_serializing_operation",
"MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
"PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches",
@@ -1945,7 +1891,7 @@
{
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
"MetricExpr": "L1D_PEND_MISS.L2_STALL / tma_info_thread_clks",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group",
+ "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group",
"MetricName": "tma_sq_full",
"MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth",
@@ -1973,7 +1919,7 @@
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
"MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group",
+ "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group",
"MetricName": "tma_store_latency",
"MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency",
@@ -2016,7 +1962,7 @@
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
"MetricExpr": "10 * BACLEARS.ANY / tma_info_thread_clks",
- "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
"MetricName": "tma_unknown_branches",
"MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
index 875b584b8443..32a3dedb82fb 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Number of machine clears due to memory ordering conflicts.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
+ "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -29,6 +32,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
+ "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -41,6 +45,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
+ "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -53,6 +58,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
+ "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -65,6 +71,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
+ "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -77,6 +84,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
+ "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -89,6 +97,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
+ "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -101,6 +110,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
+ "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -113,6 +123,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -122,6 +133,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -131,6 +143,7 @@
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -140,6 +153,7 @@
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -149,6 +163,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -158,6 +173,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -167,6 +183,7 @@
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -176,6 +193,7 @@
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -185,6 +203,7 @@
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -194,6 +213,7 @@
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -203,6 +223,7 @@
},
{
"BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ITOM.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -212,6 +233,7 @@
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -221,6 +243,7 @@
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -230,6 +253,7 @@
},
{
"BriefDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PREFETCHES.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -239,6 +263,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -248,6 +273,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -257,6 +283,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
"MSRIndex": "0x1a6,0x1a7",
@@ -266,6 +293,7 @@
},
{
"BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -275,6 +303,7 @@
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -284,6 +313,7 @@
},
{
"BriefDescription": "Counts demand data read requests that miss the L3 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"SampleAfterValue": "100003",
@@ -291,6 +321,7 @@
},
{
"BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
@@ -300,6 +331,7 @@
},
{
"BriefDescription": "This event is deprecated.",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
@@ -308,6 +340,7 @@
},
{
"BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.",
+ "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
@@ -317,6 +350,7 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@@ -326,6 +360,7 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
"PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -334,6 +369,7 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
"PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -342,6 +378,7 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
"PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
@@ -350,6 +387,7 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
"PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
@@ -358,6 +396,7 @@
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Counts the number of times RTM commit succeeded.",
@@ -366,6 +405,7 @@
},
{
"BriefDescription": "Number of times an RTM execution started.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
@@ -374,6 +414,7 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
@@ -382,6 +423,7 @@
},
{
"BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -390,6 +432,7 @@
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_READ",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
@@ -398,6 +441,7 @@
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
@@ -406,6 +450,7 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/metricgroups.json b/tools/perf/pmu-events/arch/x86/icelakex/metricgroups.json
index 904d299c95a3..cccfcab3425e 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/metricgroups.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/metricgroups.json
@@ -5,7 +5,20 @@
"BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/perf/pmu-events/arch/x86/icelakex/other.json
index 11810daaf150..05b348d9c838 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.",
@@ -25,6 +28,7 @@
},
{
"BriefDescription": "Hit snoop reply with data, line invalidated.",
+ "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.I_FWD_FE",
"PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core.",
@@ -33,6 +37,7 @@
},
{
"BriefDescription": "HitM snoop reply with data, line invalidated.",
+ "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.I_FWD_M",
"PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core.",
@@ -41,6 +46,7 @@
},
{
"BriefDescription": "Hit snoop reply without sending the data, line invalidated.",
+ "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.I_HIT_FSE",
"PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core.",
@@ -49,6 +55,7 @@
},
{
"BriefDescription": "Line not found snoop reply",
+ "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.MISS",
"PublicDescription": "Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core.",
@@ -57,6 +64,7 @@
},
{
"BriefDescription": "Hit snoop reply with data, line kept in Shared state.",
+ "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.S_FWD_FE",
"PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A single snoop response from the core counts on all hyperthreads of the core.",
@@ -65,6 +73,7 @@
},
{
"BriefDescription": "HitM snoop reply with data, line kept in Shared state",
+ "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.S_FWD_M",
"PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state. A single snoop response from the core counts on all hyperthreads of the core.",
@@ -73,6 +82,7 @@
},
{
"BriefDescription": "Hit snoop reply without sending the data, line kept in Shared state.",
+ "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.S_HIT_FSE",
"PublicDescription": "Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state. A single snoop response from the core counts on all hyperthreads of the core.",
@@ -81,6 +91,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -90,6 +101,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -99,6 +111,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -108,6 +121,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -117,6 +131,7 @@
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -126,6 +141,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -135,6 +151,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -144,6 +161,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -153,6 +171,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -162,6 +181,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -171,6 +191,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -180,6 +201,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -189,6 +211,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -198,6 +221,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -207,6 +231,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -216,6 +241,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -225,6 +251,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.LOCAL_PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -234,6 +261,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -243,6 +271,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -252,6 +281,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -261,6 +291,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -270,6 +301,7 @@
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -279,6 +311,7 @@
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -288,6 +321,7 @@
},
{
"BriefDescription": "Counts hardware prefetch (which bring data to L2) that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -297,6 +331,7 @@
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -306,6 +341,7 @@
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
@@ -315,6 +351,7 @@
},
{
"BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ITOM.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
@@ -324,6 +361,7 @@
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -333,6 +371,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -342,6 +381,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -351,6 +391,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -360,6 +401,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -369,6 +411,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -378,6 +421,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -387,6 +431,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
@@ -396,6 +441,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -405,6 +451,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY",
"MSRIndex": "0x1a6,0x1a7",
@@ -414,6 +461,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -423,6 +471,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -432,6 +481,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
@@ -441,6 +491,7 @@
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -450,6 +501,7 @@
},
{
"BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.WRITE_ESTIMATE.MEMORY",
"MSRIndex": "0x1a6,0x1a7",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
index 45ee6bceba7f..74285b6c81e7 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_ACTIVE",
@@ -10,6 +11,7 @@
},
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
@@ -18,6 +20,7 @@
},
{
"BriefDescription": "All branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -26,6 +29,7 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PEBS": "1",
@@ -35,6 +39,7 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
"PEBS": "1",
@@ -44,6 +49,7 @@
},
{
"BriefDescription": "Taken conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PEBS": "1",
@@ -53,6 +59,7 @@
},
{
"BriefDescription": "Far branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
@@ -62,6 +69,7 @@
},
{
"BriefDescription": "Indirect near branch instructions retired (excluding returns)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PEBS": "1",
@@ -71,6 +79,7 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -80,6 +89,7 @@
},
{
"BriefDescription": "Return instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -89,6 +99,7 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -98,6 +109,7 @@
},
{
"BriefDescription": "All mispredicted branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -106,6 +118,7 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PEBS": "1",
@@ -115,6 +128,7 @@
},
{
"BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
"PEBS": "1",
@@ -124,6 +138,7 @@
},
{
"BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PEBS": "1",
@@ -133,6 +148,7 @@
},
{
"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PEBS": "1",
@@ -142,6 +158,7 @@
},
{
"BriefDescription": "Mispredicted indirect CALL instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PEBS": "1",
@@ -151,6 +168,7 @@
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -160,6 +178,7 @@
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
@@ -169,6 +188,7 @@
},
{
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
"PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
@@ -177,6 +197,7 @@
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
@@ -185,6 +206,7 @@
},
{
"BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
"PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
@@ -193,6 +215,7 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
+ "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
@@ -200,6 +223,7 @@
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
@@ -208,6 +232,7 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
+ "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -215,6 +240,7 @@
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -222,6 +248,7 @@
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -230,6 +257,7 @@
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -238,6 +266,7 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -246,6 +275,7 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -254,6 +284,7 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -262,6 +293,7 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "20",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -270,6 +302,7 @@
},
{
"BriefDescription": "Total execution stalls.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -278,6 +311,7 @@
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
@@ -286,6 +320,7 @@
},
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -294,6 +329,7 @@
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -302,6 +338,7 @@
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -310,6 +347,7 @@
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
@@ -319,6 +357,7 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]",
@@ -327,6 +366,7 @@
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "INST_DECODED.DECODERS",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
@@ -335,6 +375,7 @@
},
{
"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
+ "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
@@ -343,6 +384,7 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
@@ -351,6 +393,7 @@
},
{
"BriefDescription": "Number of all retired NOP instructions.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.NOP",
"PEBS": "1",
@@ -359,6 +402,7 @@
},
{
"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution",
+ "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "1",
"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
@@ -367,6 +411,7 @@
},
{
"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.ALL_RECOVERY_CYCLES",
@@ -376,6 +421,7 @@
},
{
"BriefDescription": "Clears speculative count",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x0D",
@@ -386,6 +432,7 @@
},
{
"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
"PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
@@ -394,6 +441,7 @@
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
"PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
@@ -402,6 +450,7 @@
},
{
"BriefDescription": "TMA slots where uops got dropped",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.UOP_DROPPING",
"PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
@@ -410,6 +459,7 @@
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -418,6 +468,7 @@
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
@@ -426,6 +477,7 @@
},
{
"BriefDescription": "False dependencies due to partial compare on address.",
+ "Counter": "0,1,2,3",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.",
@@ -434,6 +486,7 @@
},
{
"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
@@ -442,6 +495,7 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -451,6 +505,7 @@
},
{
"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
+ "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_OK",
@@ -460,6 +515,7 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
+ "Counter": "0,1,2,3",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
@@ -468,6 +524,7 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
@@ -478,6 +535,7 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -486,6 +544,7 @@
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.LBR_INSERTS",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.",
@@ -494,6 +553,7 @@
},
{
"BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.PAUSE_INST",
"PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
@@ -502,6 +562,7 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
@@ -510,6 +571,7 @@
},
{
"BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SCOREBOARD",
"SampleAfterValue": "100003",
@@ -517,6 +579,7 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5e",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
@@ -525,6 +588,7 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -536,6 +600,7 @@
},
{
"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
"PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
@@ -544,6 +609,7 @@
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
+ "Counter": "Fixed counter 3",
"EventName": "TOPDOWN.SLOTS",
"PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
"SampleAfterValue": "10000003",
@@ -551,6 +617,7 @@
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.SLOTS_P",
"PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
@@ -559,6 +626,7 @@
},
{
"BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UOPS_DECODED.DEC0",
"PublicDescription": "Uops exclusively fetched by decoder 0",
@@ -567,6 +635,7 @@
},
{
"BriefDescription": "Number of uops executed on port 0",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_0",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
@@ -575,6 +644,7 @@
},
{
"BriefDescription": "Number of uops executed on port 1",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_1",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
@@ -583,6 +653,7 @@
},
{
"BriefDescription": "Number of uops executed on port 2 and 3",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_2_3",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
@@ -591,6 +662,7 @@
},
{
"BriefDescription": "Number of uops executed on port 4 and 9",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_4_9",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
@@ -599,6 +671,7 @@
},
{
"BriefDescription": "Number of uops executed on port 5",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_5",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
@@ -607,6 +680,7 @@
},
{
"BriefDescription": "Number of uops executed on port 6",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_6",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
@@ -615,6 +689,7 @@
},
{
"BriefDescription": "Number of uops executed on port 7 and 8",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_7_8",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
@@ -623,6 +698,7 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -632,6 +708,7 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -641,6 +718,7 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -650,6 +728,7 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -659,6 +738,7 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1",
@@ -668,6 +748,7 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2",
@@ -677,6 +758,7 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3",
@@ -686,6 +768,7 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4",
@@ -695,6 +778,7 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -705,6 +789,7 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.THREAD",
"SampleAfterValue": "2000003",
@@ -712,6 +797,7 @@
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.X87",
"PublicDescription": "Counts the number of x87 uops executed.",
@@ -720,6 +806,7 @@
},
{
"BriefDescription": "Uops that RAT issues to RS",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
@@ -728,6 +815,7 @@
},
{
"BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -738,6 +826,7 @@
},
{
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide.",
@@ -746,6 +835,7 @@
},
{
"BriefDescription": "Retirement slots used.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.SLOTS",
"PublicDescription": "Counts the retirement slots used each cycle.",
@@ -754,6 +844,7 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -764,6 +855,7 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "10",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json
index a950ba3ddcb4..8c73708befef 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json
@@ -1,80 +1,98 @@
[
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x65",
"EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x65",
"EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x65",
"EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x64",
"EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x64",
"EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x64",
"EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x70",
"EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x70",
"EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -82,8 +100,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -91,8 +111,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -100,8 +122,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -109,8 +133,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -118,8 +144,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -127,8 +155,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -136,8 +166,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -145,8 +177,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -154,8 +188,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -163,8 +199,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -172,8 +210,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -181,8 +221,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -190,8 +232,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -199,8 +243,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -208,8 +254,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -217,8 +265,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -226,8 +276,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -235,8 +287,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -244,8 +298,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -253,8 +309,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -262,8 +320,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -271,8 +331,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -280,8 +342,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -289,8 +353,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -298,8 +364,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -307,8 +375,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -316,8 +386,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -325,8 +397,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -334,8 +408,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -343,8 +419,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -352,8 +430,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -361,8 +441,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -370,8 +452,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -379,8 +463,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -388,8 +474,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -397,8 +485,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -406,8 +496,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -415,8 +507,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -424,8 +518,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -433,8 +529,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -442,8 +540,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -451,8 +551,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -460,8 +562,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -469,8 +573,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -478,8 +584,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -487,8 +595,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -496,8 +606,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -505,8 +617,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -514,8 +628,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -523,8 +639,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -532,8 +650,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -541,8 +661,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -550,8 +672,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -559,8 +683,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -568,8 +694,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -577,8 +705,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -586,8 +716,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -595,8 +727,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -604,8 +738,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -613,8 +749,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -622,8 +760,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -631,8 +771,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -640,8 +782,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -649,8 +793,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -658,8 +804,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -667,8 +815,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -676,8 +826,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -685,8 +837,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -694,8 +848,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -703,8 +859,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -712,8 +870,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -721,8 +881,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -730,8 +892,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -739,8 +903,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -748,8 +914,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -757,8 +925,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -766,8 +936,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -775,8 +947,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -784,8 +958,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -793,8 +969,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -802,8 +980,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -811,8 +991,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -820,8 +1002,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -829,8 +1013,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -838,8 +1024,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -847,8 +1035,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -856,8 +1046,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -865,8 +1057,10 @@
},
{
"BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.",
"UMask": "0x2",
@@ -874,8 +1068,10 @@
},
{
"BriefDescription": "CHA to iMC Bypass : Not Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
"UMask": "0x4",
@@ -883,8 +1079,10 @@
},
{
"BriefDescription": "CHA to iMC Bypass : Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.",
"UMask": "0x1",
@@ -892,12 +1090,14 @@
},
{
"BriefDescription": "Clockticks of the uncore caching and home agent (CHA)",
+ "Counter": "0,1,2,3",
"EventName": "UNC_CHA_CLOCKTICKS",
"PerPkg": "1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_CHA_CMS_CLOCKTICKS",
"PerPkg": "1",
@@ -905,8 +1105,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0xf2",
@@ -914,8 +1116,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0xf1",
@@ -923,8 +1127,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x42",
@@ -932,8 +1138,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x41",
@@ -941,8 +1149,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x82",
@@ -950,8 +1160,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Single Eviction",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x81",
@@ -959,8 +1171,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x22",
@@ -968,8 +1182,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x21",
@@ -977,8 +1193,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x12",
@@ -986,8 +1204,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x11",
@@ -995,104 +1215,130 @@
},
{
"BriefDescription": "Counter 0 Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that did not have to send any snoops because the directory was clean.",
"UMask": "0x2",
@@ -1100,8 +1346,10 @@
},
{
"BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that had to send one or more snoops because the directory was not clean.",
"UMask": "0x1",
@@ -1109,6 +1357,7 @@
},
{
"BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_CHA_DIR_UPDATE.HA",
"PerPkg": "1",
@@ -1118,6 +1367,7 @@
},
{
"BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from (table of requests) TOR pipe",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_CHA_DIR_UPDATE.TOR",
"PerPkg": "1",
@@ -1127,8 +1377,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Local",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
"UMask": "0x4",
@@ -1136,8 +1388,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
"UMask": "0x8",
@@ -1145,8 +1399,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
"UMask": "0x40",
@@ -1154,8 +1410,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
@@ -1163,8 +1421,10 @@
},
{
"BriefDescription": "Distress signal asserted : Horizontal",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x2",
@@ -1172,8 +1432,10 @@
},
{
"BriefDescription": "Distress signal asserted : PMM Local",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x10",
@@ -1181,8 +1443,10 @@
},
{
"BriefDescription": "Distress signal asserted : PMM Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x20",
@@ -1190,8 +1454,10 @@
},
{
"BriefDescription": "Distress signal asserted : Vertical",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x1",
@@ -1199,8 +1465,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x4",
@@ -1208,8 +1476,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x1",
@@ -1217,8 +1487,10 @@
},
{
"BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_CHA_HITME_HIT.EX_RDS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).",
"UMask": "0x1",
@@ -1226,8 +1498,10 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state. : Shared hit and op is RdInvOwn, RdInv, Inv*",
"UMask": "0x4",
@@ -1235,16 +1509,20 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_CHA_HITME_HIT.WBMTOE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
"UMask": "0x10",
@@ -1252,8 +1530,10 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_CHA_HITME_LOOKUP.READ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
"UMask": "0x1",
@@ -1261,8 +1541,10 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
"UMask": "0x2",
@@ -1270,8 +1552,10 @@
},
{
"BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line : No SF/LLC HitS/F and op is RdInvOwn",
"UMask": "0x40",
@@ -1279,8 +1563,10 @@
},
{
"BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
"UMask": "0x80",
@@ -1288,8 +1574,10 @@
},
{
"BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line : SF/LLC HitS/F and op is RdInvOwn",
"UMask": "0x20",
@@ -1297,16 +1585,20 @@
},
{
"BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HitME$ on Reads without RspFwdI*",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry",
"UMask": "0x1",
@@ -1314,16 +1606,20 @@
},
{
"BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request",
"UMask": "0x2",
@@ -1331,16 +1627,20 @@
},
{
"BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_CHA_HITME_UPDATE.SHARED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -1348,8 +1648,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -1357,8 +1659,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -1366,8 +1670,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -1375,8 +1681,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -1384,8 +1692,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -1393,8 +1703,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -1402,8 +1714,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -1411,8 +1725,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -1420,8 +1736,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -1429,8 +1747,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -1438,8 +1758,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -1447,8 +1769,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -1456,8 +1780,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -1465,8 +1791,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -1474,8 +1802,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -1483,8 +1813,10 @@
},
{
"BriefDescription": "Horizontal IV Ring in Use : Left",
+ "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
@@ -1492,8 +1824,10 @@
},
{
"BriefDescription": "Horizontal IV Ring in Use : Right",
+ "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
@@ -1501,6 +1835,7 @@
},
{
"BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
"PerPkg": "1",
@@ -1510,8 +1845,10 @@
},
{
"BriefDescription": "HA to iMC Reads Issued : ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.",
"UMask": "0x2",
@@ -1519,6 +1856,7 @@
},
{
"BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
"PerPkg": "1",
@@ -1528,8 +1866,10 @@
},
{
"BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.",
"UMask": "0x4",
@@ -1537,8 +1877,10 @@
},
{
"BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.",
"UMask": "0x2",
@@ -1546,8 +1888,10 @@
},
{
"BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.",
"UMask": "0x8",
@@ -1555,8 +1899,10 @@
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
"UMask": "0x1fffff",
@@ -1564,8 +1910,10 @@
},
{
"BriefDescription": "Cache Lookups : All transactions from Remote Agents",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1e20ff",
@@ -1573,34 +1921,42 @@
},
{
"BriefDescription": "Cache Lookups : All Request Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated.",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1bd0ff",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x19d0ff",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Code Reads",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1bd0ff",
@@ -1608,16 +1964,20 @@
},
{
"BriefDescription": "Cache Lookups : CRd Request Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"UMask": "0x19d0ff",
@@ -1625,8 +1985,10 @@
},
{
"BriefDescription": "Cache Lookups : Code Read Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1bd001",
@@ -1634,8 +1996,10 @@
},
{
"BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"UMask": "0x1a10ff",
@@ -1643,32 +2007,39 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1a10ff",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Local request Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1bc1ff",
"Unit": "CHA"
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
@@ -1678,25 +2049,31 @@
},
{
"BriefDescription": "This event is deprecated.",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1fc1ff",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Data Read Request Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Read transactions.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
"UMask": "0x19c1ff",
@@ -1704,8 +2081,10 @@
},
{
"BriefDescription": "Cache Lookups : Data Read Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1bc101",
@@ -1713,8 +2092,10 @@
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
"UMask": "0x1a01ff",
@@ -1722,17 +2103,21 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x841ff",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : E State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Exclusive State",
"UMask": "0x20",
@@ -1740,8 +2125,10 @@
},
{
"BriefDescription": "Cache Lookups : F State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Forward State",
"UMask": "0x80",
@@ -1749,8 +2136,10 @@
},
{
"BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
"UMask": "0x1a44ff",
@@ -1758,8 +2147,10 @@
},
{
"BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
"UMask": "0x1844ff",
@@ -1767,8 +2158,10 @@
},
{
"BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
"UMask": "0x1a04ff",
@@ -1776,16 +2169,20 @@
},
{
"BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.I",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Miss",
"UMask": "0x1",
@@ -1793,8 +2190,10 @@
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
"UMask": "0x189dff",
@@ -1802,42 +2201,52 @@
},
{
"BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x189dff",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xbdfff",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Transactions homed locally Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Transactions homed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
"UMask": "0xbdfff",
@@ -1845,8 +2254,10 @@
},
{
"BriefDescription": "Cache Lookups : M State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.M",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Modified State",
"UMask": "0x40",
@@ -1854,8 +2265,10 @@
},
{
"BriefDescription": "Cache Lookups : All Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1fe001",
@@ -1863,24 +2276,30 @@
},
{
"BriefDescription": "Cache Lookups : Write Request Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Writeback transactions to the LLC This includes all write transactions -- both Cacheable and UC.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Remote non-snoop request Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Remote non-snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Non-snoop transactions to the LLC from remote agent",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Reads",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.READ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1bd9ff",
@@ -1888,8 +2307,10 @@
},
{
"BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x9d9ff",
@@ -1897,8 +2318,10 @@
},
{
"BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x11d9ff",
@@ -1906,8 +2329,10 @@
},
{
"BriefDescription": "Cache Lookups : Read Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1bd901",
@@ -1915,8 +2340,10 @@
},
{
"BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0xbd901",
@@ -1924,8 +2351,10 @@
},
{
"BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x13d901",
@@ -1933,8 +2362,10 @@
},
{
"BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x161901",
@@ -1942,8 +2373,10 @@
},
{
"BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0xa19ff",
@@ -1951,8 +2384,10 @@
},
{
"BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1bd90e",
@@ -1960,33 +2395,41 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x15dfff",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Transactions homed remotely Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Transactions homed remotely Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Remote snoop request Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Remote snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Snoop transactions to the LLC from remote agent",
"Unit": "CHA"
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
"UMask": "0x1c19ff",
@@ -1994,8 +2437,10 @@
},
{
"BriefDescription": "Cache Lookups : Transactions homed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
"UMask": "0x15dfff",
@@ -2003,8 +2448,10 @@
},
{
"BriefDescription": "Cache Lookups : RFO Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"UMask": "0x1bc8ff",
@@ -2012,16 +2459,20 @@
},
{
"BriefDescription": "Cache Lookups : RFO Request Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"UMask": "0x19c8ff",
@@ -2029,8 +2480,10 @@
},
{
"BriefDescription": "Cache Lookups : RFO Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1bc801",
@@ -2038,17 +2491,21 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x888ff",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"UMask": "0x1a08ff",
@@ -2056,8 +2513,10 @@
},
{
"BriefDescription": "Cache Lookups : S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Shared State",
"UMask": "0x10",
@@ -2065,8 +2524,10 @@
},
{
"BriefDescription": "Cache Lookups : SnoopFilter - E State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Exclusive State",
"UMask": "0x4",
@@ -2074,8 +2535,10 @@
},
{
"BriefDescription": "Cache Lookups : SnoopFilter - H State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit HitMe State",
"UMask": "0x8",
@@ -2083,8 +2546,10 @@
},
{
"BriefDescription": "Cache Lookups : SnoopFilter - S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Shared State",
"UMask": "0x2",
@@ -2092,8 +2557,10 @@
},
{
"BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.",
"UMask": "0x1a42ff",
@@ -2101,24 +2568,29 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x842ff",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x17c2ff",
"Unit": "CHA"
},
{
"BriefDescription": "Lines Victimized : All Lines Victimized",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.ALL",
"PerPkg": "1",
@@ -2128,8 +2600,10 @@
},
{
"BriefDescription": "Lines Victimized : Lines in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x2",
@@ -2137,8 +2611,10 @@
},
{
"BriefDescription": "Lines Victimized : Local - All Lines",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x200f",
@@ -2146,8 +2622,10 @@
},
{
"BriefDescription": "Lines Victimized : Local - Lines in E State",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x2002",
@@ -2155,8 +2633,10 @@
},
{
"BriefDescription": "Lines Victimized : Local - Lines in M State",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x2001",
@@ -2164,16 +2644,20 @@
},
{
"BriefDescription": "Lines Victimized : Local Only",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"Unit": "CHA"
},
{
"BriefDescription": "Lines Victimized : Local - Lines in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x2004",
@@ -2181,8 +2665,10 @@
},
{
"BriefDescription": "Lines Victimized : Lines in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x1",
@@ -2190,8 +2676,10 @@
},
{
"BriefDescription": "Lines Victimized : Remote - All Lines",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Remote - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x800f",
@@ -2199,8 +2687,10 @@
},
{
"BriefDescription": "Lines Victimized : Remote - Lines in E State",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Remote - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x8002",
@@ -2208,8 +2698,10 @@
},
{
"BriefDescription": "Lines Victimized : Remote - Lines in M State",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Remote - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x8001",
@@ -2217,16 +2709,20 @@
},
{
"BriefDescription": "Lines Victimized : Remote Only",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"Unit": "CHA"
},
{
"BriefDescription": "Lines Victimized : Remote - Lines in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Remote - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x8004",
@@ -2234,8 +2730,10 @@
},
{
"BriefDescription": "Lines Victimized : Lines in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x4",
@@ -2243,8 +2741,10 @@
},
{
"BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.",
"UMask": "0x20",
@@ -2252,8 +2752,10 @@
},
{
"BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.",
"UMask": "0x10",
@@ -2261,8 +2763,10 @@
},
{
"BriefDescription": "Number of times that an RFO hit in S state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_CHA_MISC.RFO_HIT_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.",
"UMask": "0x8",
@@ -2270,8 +2774,10 @@
},
{
"BriefDescription": "Cbo Misc : Silent Snoop Eviction",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.",
"UMask": "0x1",
@@ -2279,8 +2785,10 @@
},
{
"BriefDescription": "Cbo Misc : Write Combining Aliasing",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_CHA_MISC.WC_ALIASING",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.",
"UMask": "0x2",
@@ -2288,24 +2796,30 @@
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x1",
@@ -2313,8 +2827,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : Local Rd",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.LOCAL_READ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x2",
@@ -2322,8 +2838,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : Off",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x20",
@@ -2331,8 +2849,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : Remote Rd",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.REMOTE_READ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x4",
@@ -2340,8 +2860,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.REMOTE_READINVITOE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x8",
@@ -2349,8 +2871,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x10",
@@ -2358,48 +2882,60 @@
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"UMask": "0x4",
@@ -2407,8 +2943,10 @@
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"UMask": "0x10",
@@ -2416,8 +2954,10 @@
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"UMask": "0x2",
@@ -2425,8 +2965,10 @@
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"UMask": "0x8",
@@ -2434,32 +2976,40 @@
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"UMask": "0x20",
@@ -2467,80 +3017,100 @@
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"UMask": "0x40",
@@ -2548,8 +3118,10 @@
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"UMask": "0x80",
@@ -2557,8 +3129,10 @@
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"UMask": "0x1",
@@ -2566,128 +3140,130 @@
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
- "PerPkg": "1",
- "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Pipe Rejects",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
- "PerPkg": "1",
- "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
- "PerPkg": "1",
- "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Pipe Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the LLC.",
"UMask": "0x2",
@@ -2695,8 +3271,10 @@
},
{
"BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the SF.",
"UMask": "0x1",
@@ -2704,8 +3282,10 @@
},
{
"BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR",
+ "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR : No Reject in the CHA due to a pending read to the same near memory set in the TOR.",
"UMask": "0x4",
@@ -2713,88 +3293,110 @@
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.REJ_IRQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.THROTTLE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": count # of FAST TOR Request inserted to ha_tor_req_fifo",
"UMask": "0x2",
@@ -2802,8 +3404,10 @@
},
{
"BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": count # of SLOW TOR Request inserted to ha_pmm_tor_req_fifo",
"UMask": "0x1",
@@ -2811,8 +3415,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.",
"UMask": "0x1",
@@ -2820,8 +3426,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.",
"UMask": "0x2",
@@ -2829,40 +3437,50 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only.",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only.",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only.",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only.",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.",
"UMask": "0x4",
@@ -2870,8 +3488,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.",
"UMask": "0x8",
@@ -2879,8 +3499,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.",
"UMask": "0x10",
@@ -2888,8 +3510,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.",
"UMask": "0x20",
@@ -2897,8 +3521,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only.",
"UMask": "0x40",
@@ -2906,8 +3532,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only.",
"UMask": "0x80",
@@ -2915,24 +3543,30 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only.",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only.",
"Unit": "CHA"
},
{
"BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.INVITOE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
"UMask": "0x30",
@@ -2940,6 +3574,7 @@
},
{
"BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
@@ -2949,6 +3584,7 @@
},
{
"BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
@@ -2958,6 +3594,7 @@
},
{
"BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.READS",
"PerPkg": "1",
@@ -2967,6 +3604,7 @@
},
{
"BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
"PerPkg": "1",
@@ -2976,6 +3614,7 @@
},
{
"BriefDescription": "Remote read requests sent to the CHA's home agent",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
"PerPkg": "1",
@@ -2985,6 +3624,7 @@
},
{
"BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.WRITES",
"PerPkg": "1",
@@ -2994,6 +3634,7 @@
},
{
"BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
@@ -3003,6 +3644,7 @@
},
{
"BriefDescription": "Remote write requests sent to the CHA's home agent",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
@@ -3012,8 +3654,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x1",
@@ -3021,8 +3665,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x2",
@@ -3030,8 +3676,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x4",
@@ -3039,8 +3687,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x8",
@@ -3048,8 +3698,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x1",
@@ -3057,8 +3709,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x2",
@@ -3066,8 +3720,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x10",
@@ -3075,8 +3731,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x4",
@@ -3084,8 +3742,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x8",
@@ -3093,95 +3753,119 @@
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Source Throttle",
+ "Counter": "0,1,2,3",
"EventCode": "0xae",
"EventName": "UNC_CHA_RING_SRC_THRTL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress (from CMS) Allocations : IPQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.IPQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x4",
@@ -3189,8 +3873,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : IRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x1",
@@ -3198,8 +3884,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x2",
@@ -3207,8 +3895,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x10",
@@ -3216,8 +3906,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x20",
@@ -3225,8 +3917,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : RRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.RRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x40",
@@ -3234,8 +3928,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : WBQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.WBQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x80",
@@ -3243,8 +3939,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -3252,8 +3950,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -3261,8 +3961,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
"UMask": "0x40",
@@ -3270,8 +3972,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -3279,8 +3983,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -3288,8 +3994,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -3297,8 +4005,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -3306,8 +4016,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
"UMask": "0x80",
@@ -3315,16 +4027,20 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true",
"UMask": "0x1",
@@ -3332,16 +4048,20 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -3349,16 +4069,20 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -3366,8 +4090,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -3375,16 +4101,20 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -3392,8 +4122,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -3401,8 +4133,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
"UMask": "0x40",
@@ -3410,8 +4144,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -3419,8 +4155,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -3428,8 +4166,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -3437,8 +4177,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -3446,8 +4188,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
"UMask": "0x80",
@@ -3455,16 +4199,20 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true",
"UMask": "0x1",
@@ -3472,16 +4220,20 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -3489,24 +4241,30 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CHA"
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -3514,16 +4272,20 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -3531,8 +4293,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -3540,8 +4304,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
"UMask": "0x40",
@@ -3549,8 +4315,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -3558,8 +4326,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -3567,8 +4337,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -3576,8 +4348,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -3585,8 +4359,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
"UMask": "0x80",
@@ -3594,8 +4370,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -3603,8 +4381,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -3612,8 +4392,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
"UMask": "0x40",
@@ -3621,8 +4403,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -3630,8 +4414,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -3639,8 +4425,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -3648,8 +4436,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -3657,8 +4447,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
"UMask": "0x80",
@@ -3666,8 +4458,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
"UMask": "0x1",
@@ -3675,8 +4469,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
"UMask": "0x2",
@@ -3684,8 +4480,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
"UMask": "0x1",
@@ -3693,8 +4491,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
"UMask": "0x2",
@@ -3702,8 +4502,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Occupancy : IPQ",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x4",
@@ -3711,8 +4513,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x1",
@@ -3720,8 +4524,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Occupancy : RRQ",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x40",
@@ -3729,8 +4535,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Occupancy : WBQ",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x80",
@@ -3738,8 +4546,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -3747,8 +4557,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -3756,8 +4568,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message",
"UMask": "0x40",
@@ -3765,8 +4579,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -3774,8 +4590,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -3783,8 +4601,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -3792,8 +4612,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -3801,8 +4623,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message",
"UMask": "0x80",
@@ -3810,8 +4634,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x40",
@@ -3819,8 +4645,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true",
"UMask": "0x1",
@@ -3828,8 +4656,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x2",
@@ -3837,8 +4667,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -3846,8 +4678,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x4",
@@ -3855,8 +4689,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -3864,8 +4700,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -3873,8 +4711,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x10",
@@ -3882,8 +4722,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -3891,8 +4733,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -3900,8 +4744,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
"UMask": "0x40",
@@ -3909,8 +4755,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -3918,8 +4766,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -3927,8 +4777,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -3936,8 +4788,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -3945,8 +4799,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
"UMask": "0x80",
@@ -3954,16 +4810,20 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true",
"UMask": "0x1",
@@ -3971,16 +4831,20 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -3988,16 +4852,20 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -4005,8 +4873,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -4014,16 +4884,20 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -4031,8 +4905,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -4040,8 +4916,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message",
"UMask": "0x40",
@@ -4049,8 +4927,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -4058,8 +4938,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -4067,8 +4949,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -4076,8 +4960,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -4085,8 +4971,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message",
"UMask": "0x80",
@@ -4094,8 +4982,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x40",
@@ -4103,8 +4993,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true",
"UMask": "0x1",
@@ -4112,8 +5004,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x2",
@@ -4121,8 +5015,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -4130,8 +5026,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x4",
@@ -4139,8 +5037,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -4148,8 +5048,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -4157,8 +5059,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x10",
@@ -4166,8 +5070,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -4175,8 +5081,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -4184,8 +5092,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message",
"UMask": "0x40",
@@ -4193,8 +5103,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -4202,8 +5114,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -4211,8 +5125,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -4220,8 +5136,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -4229,8 +5147,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message",
"UMask": "0x80",
@@ -4238,8 +5158,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
"UMask": "0x40",
@@ -4247,8 +5169,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true",
"UMask": "0x1",
@@ -4256,8 +5180,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
"UMask": "0x2",
@@ -4265,8 +5191,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -4274,8 +5202,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
"UMask": "0x4",
@@ -4283,8 +5213,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -4292,8 +5224,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -4301,8 +5235,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
"UMask": "0x10",
@@ -4310,8 +5246,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -4319,8 +5257,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -4328,8 +5268,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message",
"UMask": "0x40",
@@ -4337,8 +5279,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -4346,8 +5290,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -4355,8 +5301,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -4364,8 +5312,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -4373,8 +5323,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message",
"UMask": "0x80",
@@ -4382,8 +5334,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x40",
@@ -4391,8 +5345,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true",
"UMask": "0x1",
@@ -4400,8 +5356,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x2",
@@ -4409,8 +5367,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -4418,8 +5378,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x4",
@@ -4427,8 +5389,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -4436,8 +5400,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -4445,8 +5411,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x10",
@@ -4454,8 +5422,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x11",
@@ -4463,8 +5433,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
@@ -4472,8 +5444,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x1",
@@ -4481,8 +5455,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x44",
@@ -4490,8 +5466,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
@@ -4499,8 +5477,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x4",
@@ -4508,8 +5488,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
@@ -4517,8 +5499,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x10",
@@ -4526,8 +5510,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x1",
@@ -4535,8 +5521,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_CHA_RxR_BYPASS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
"UMask": "0x2",
@@ -4544,8 +5532,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x80",
@@ -4553,8 +5543,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x44",
@@ -4562,8 +5554,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x40",
@@ -4571,8 +5565,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x4",
@@ -4580,8 +5576,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_CHA_RxR_BYPASS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
"UMask": "0x8",
@@ -4589,8 +5587,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -4598,8 +5598,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x10",
@@ -4607,8 +5609,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x1",
@@ -4616,8 +5620,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x2",
@@ -4625,8 +5631,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -4634,8 +5642,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x40",
@@ -4643,8 +5653,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x4",
@@ -4652,8 +5664,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x80",
@@ -4661,8 +5675,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x8",
@@ -4670,16 +5686,20 @@
},
{
"BriefDescription": "Transgress Injection Starvation",
+ "Counter": "0,1,2,3",
"EventCode": "0xe4",
"EventName": "UNC_CHA_RxR_CRD_STARVED_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
@@ -4687,8 +5707,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
@@ -4696,8 +5718,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
@@ -4705,8 +5729,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_CHA_RxR_INSERTS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
@@ -4714,8 +5740,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
@@ -4723,8 +5751,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
@@ -4732,8 +5762,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x40",
@@ -4741,8 +5773,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
@@ -4750,8 +5784,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_CHA_RxR_INSERTS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
@@ -4759,8 +5795,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
@@ -4768,8 +5806,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
@@ -4777,8 +5817,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
@@ -4786,8 +5828,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
@@ -4795,8 +5839,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
@@ -4804,8 +5850,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
@@ -4813,8 +5861,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
@@ -4822,8 +5872,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
@@ -4831,8 +5883,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
@@ -4840,6 +5894,7 @@
},
{
"BriefDescription": "Snoop filter capacity evictions for E-state entries.",
+ "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_CHA_SF_EVICTION.E_STATE",
"PerPkg": "1",
@@ -4849,6 +5904,7 @@
},
{
"BriefDescription": "Snoop filter capacity evictions for M-state entries.",
+ "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_CHA_SF_EVICTION.M_STATE",
"PerPkg": "1",
@@ -4858,6 +5914,7 @@
},
{
"BriefDescription": "Snoop filter capacity evictions for S-state entries.",
+ "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_CHA_SF_EVICTION.S_STATE",
"PerPkg": "1",
@@ -4867,8 +5924,10 @@
},
{
"BriefDescription": "Snoops Sent : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.",
"UMask": "0x1",
@@ -4876,8 +5935,10 @@
},
{
"BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests",
"UMask": "0x10",
@@ -4885,8 +5946,10 @@
},
{
"BriefDescription": "Snoops Sent : Broadcast snoops for Remote Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to remote requests",
"UMask": "0x20",
@@ -4894,8 +5957,10 @@
},
{
"BriefDescription": "Snoops Sent : Directed snoops for Local Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests",
"UMask": "0x40",
@@ -4903,8 +5968,10 @@
},
{
"BriefDescription": "Snoops Sent : Directed snoops for Remote Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to remote requests",
"UMask": "0x80",
@@ -4912,8 +5979,10 @@
},
{
"BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests",
"UMask": "0x4",
@@ -4921,8 +5990,10 @@
},
{
"BriefDescription": "Snoops Sent : Snoops sent for Remote Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to remote requests",
"UMask": "0x8",
@@ -4930,8 +6001,10 @@
},
{
"BriefDescription": "Snoop Responses Received : RSPCNFLCT*",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
@@ -4939,8 +6012,10 @@
},
{
"BriefDescription": "Snoop Responses Received : RspFwd",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
"UMask": "0x80",
@@ -4948,8 +6023,10 @@
},
{
"BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
"UMask": "0x20",
@@ -4957,8 +6034,10 @@
},
{
"BriefDescription": "Snoop Responses Received : RspI",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).",
"UMask": "0x1",
@@ -4966,8 +6045,10 @@
},
{
"BriefDescription": "Snoop Responses Received : RspIFwd",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.",
"UMask": "0x4",
@@ -4975,8 +6056,10 @@
},
{
"BriefDescription": "Snoop Responses Received : RspS",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
"UMask": "0x2",
@@ -4984,8 +6067,10 @@
},
{
"BriefDescription": "Snoop Responses Received : RspSFwd",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
"UMask": "0x8",
@@ -4993,8 +6078,10 @@
},
{
"BriefDescription": "Snoop Responses Received : Rsp*WB",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPWB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
"UMask": "0x10",
@@ -5002,8 +6089,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspCnflct",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
@@ -5011,8 +6100,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspFwd",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
"UMask": "0x80",
@@ -5020,8 +6111,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
"UMask": "0x20",
@@ -5029,8 +6122,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspI",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
"UMask": "0x1",
@@ -5038,8 +6133,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspIFwd",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
"UMask": "0x4",
@@ -5047,8 +6144,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspS",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
"UMask": "0x2",
@@ -5056,8 +6155,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspSFwd",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.",
"UMask": "0x8",
@@ -5065,8 +6166,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : Rsp*WB",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
"UMask": "0x10",
@@ -5074,56 +6177,70 @@
},
{
"BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
+ "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
+ "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
"BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
+ "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
+ "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -5131,8 +6248,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -5140,8 +6259,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -5149,8 +6270,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -5158,8 +6281,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -5167,8 +6292,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -5176,8 +6303,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -5185,8 +6314,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -5194,8 +6325,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -5203,8 +6336,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -5212,8 +6347,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -5221,8 +6358,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -5230,8 +6369,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -5239,8 +6380,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -5248,8 +6391,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -5257,8 +6402,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -5266,8 +6413,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -5275,8 +6424,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -5284,8 +6435,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -5293,8 +6446,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -5302,8 +6457,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -5311,8 +6468,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -5320,8 +6479,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -5329,8 +6490,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -5338,8 +6501,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -5347,8 +6512,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -5356,8 +6523,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -5365,8 +6534,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -5374,8 +6545,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -5383,8 +6556,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -5392,8 +6567,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -5401,8 +6578,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -5410,8 +6589,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -5419,8 +6600,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -5428,8 +6611,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -5437,8 +6622,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -5446,8 +6633,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -5455,8 +6644,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -5464,8 +6655,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -5473,8 +6666,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -5482,8 +6677,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -5491,8 +6688,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -5500,8 +6699,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -5509,8 +6710,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -5518,8 +6721,10 @@
},
{
"BriefDescription": "TOR Inserts : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc001ffff",
@@ -5527,24 +6732,30 @@
},
{
"BriefDescription": "TOR Inserts : DDR4 Access",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.DDR4",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : SF/LLC Evictions",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
"UMask": "0x2",
@@ -5552,14 +6763,17 @@
},
{
"BriefDescription": "TOR Inserts : Just Hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.HIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : All requests from iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA",
"PerPkg": "1",
@@ -5569,6 +6783,7 @@
},
{
"BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
"PerPkg": "1",
@@ -5578,8 +6793,10 @@
},
{
"BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8d7ff01",
@@ -5587,6 +6804,7 @@
},
{
"BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
"PerPkg": "1",
@@ -5596,8 +6814,10 @@
},
{
"BriefDescription": "TOR Inserts; CRd Pref from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
"UMask": "0xc88fff01",
@@ -5605,8 +6825,10 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRds issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc817ff01",
@@ -5614,8 +6836,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc837ff01",
@@ -5623,8 +6847,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc827ff01",
@@ -5632,8 +6858,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8a7ff01",
@@ -5641,6 +6869,7 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
"PerPkg": "1",
@@ -5650,6 +6879,7 @@
},
{
"BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
"PerPkg": "1",
@@ -5659,6 +6889,7 @@
},
{
"BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
"PerPkg": "1",
@@ -5668,6 +6899,7 @@
},
{
"BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
"PerPkg": "1",
@@ -5677,6 +6909,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
"PerPkg": "1",
@@ -5686,8 +6919,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc837fd01",
@@ -5695,8 +6930,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc827fd01",
@@ -5704,8 +6941,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8a7fd01",
@@ -5713,6 +6952,7 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
"PerPkg": "1",
@@ -5722,8 +6962,10 @@
},
{
"BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47fd01",
@@ -5731,8 +6973,10 @@
},
{
"BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcccffd01",
@@ -5740,17 +6984,21 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xcccffd01",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xccd7fd01",
@@ -5758,15 +7006,18 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xccd7fd01",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
"PerPkg": "1",
@@ -5776,6 +7027,7 @@
},
{
"BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
"PerPkg": "1",
@@ -5785,6 +7037,7 @@
},
{
"BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
"PerPkg": "1",
@@ -5794,8 +7047,10 @@
},
{
"BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc57fd01",
@@ -5803,8 +7058,10 @@
},
{
"BriefDescription": "TOR Inserts : ItoMs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : ItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47ff01",
@@ -5812,8 +7069,10 @@
},
{
"BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd47ff01",
@@ -5821,8 +7080,10 @@
},
{
"BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcccfff01",
@@ -5830,6 +7091,7 @@
},
{
"BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
"PerPkg": "1",
@@ -5839,6 +7101,7 @@
},
{
"BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
"PerPkg": "1",
@@ -5848,6 +7111,7 @@
},
{
"BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"PerPkg": "1",
@@ -5857,6 +7121,7 @@
},
{
"BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
"PerPkg": "1",
@@ -5866,8 +7131,10 @@
},
{
"BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc80efe01",
@@ -5875,6 +7142,7 @@
},
{
"BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
"PerPkg": "1",
@@ -5884,8 +7152,10 @@
},
{
"BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc88efe01",
@@ -5893,8 +7163,10 @@
},
{
"BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc88f7e01",
@@ -5902,8 +7174,10 @@
},
{
"BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc80f7e01",
@@ -5911,6 +7185,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
"PerPkg": "1",
@@ -5920,8 +7195,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc837fe01",
@@ -5929,6 +7206,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
"PerPkg": "1",
@@ -5938,6 +7216,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
"PerPkg": "1",
@@ -5947,6 +7226,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
"PerPkg": "1",
@@ -5956,6 +7236,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
"PerPkg": "1",
@@ -5965,8 +7246,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc827fe01",
@@ -5974,8 +7257,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8a7fe01",
@@ -5983,6 +7268,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
"PerPkg": "1",
@@ -5992,6 +7278,7 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
"PerPkg": "1",
@@ -6001,8 +7288,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8978601",
@@ -6010,6 +7299,7 @@
},
{
"BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
"PerPkg": "1",
@@ -6019,8 +7309,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8968601",
@@ -6028,8 +7320,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8968a01",
@@ -6037,8 +7331,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8978a01",
@@ -6046,6 +7342,7 @@
},
{
"BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
"PerPkg": "1",
@@ -6055,8 +7352,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8970601",
@@ -6064,8 +7363,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8970a01",
@@ -6073,6 +7374,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
"PerPkg": "1",
@@ -6082,6 +7384,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
"PerPkg": "1",
@@ -6091,6 +7394,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
"PerPkg": "1",
@@ -6100,6 +7404,7 @@
},
{
"BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
"PerPkg": "1",
@@ -6109,8 +7414,10 @@
},
{
"BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8678601",
@@ -6118,17 +7425,21 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc8678601",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8668601",
@@ -6136,17 +7447,21 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc8668601",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8668a01",
@@ -6154,8 +7469,10 @@
},
{
"BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8678a01",
@@ -6163,8 +7480,10 @@
},
{
"BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8670601",
@@ -6172,17 +7491,21 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc8670601",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8670a01",
@@ -6190,8 +7513,10 @@
},
{
"BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47fe01",
@@ -6199,8 +7524,10 @@
},
{
"BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcccffe01",
@@ -6208,6 +7535,7 @@
},
{
"BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
"PerPkg": "1",
@@ -6217,6 +7545,7 @@
},
{
"BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
"PerPkg": "1",
@@ -6226,8 +7555,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8668601",
@@ -6235,8 +7566,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8668a01",
@@ -6244,8 +7577,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86e8601",
@@ -6253,8 +7588,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86e8a01",
@@ -6262,6 +7599,7 @@
},
{
"BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
"PerPkg": "1",
@@ -6271,8 +7609,10 @@
},
{
"BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86f8601",
@@ -6280,17 +7620,21 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRAM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc86f8601",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86e8601",
@@ -6298,17 +7642,21 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc86e8601",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86e8a01",
@@ -6316,8 +7664,10 @@
},
{
"BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86f8a01",
@@ -6325,8 +7675,10 @@
},
{
"BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86f0601",
@@ -6334,17 +7686,21 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc86f0601",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86f0a01",
@@ -6352,8 +7708,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8670601",
@@ -6361,8 +7719,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8670a01",
@@ -6370,8 +7730,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f0601",
@@ -6379,8 +7741,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f0a01",
@@ -6388,6 +7752,7 @@
},
{
"BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
"PerPkg": "1",
@@ -6397,6 +7762,7 @@
},
{
"BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
"PerPkg": "1",
@@ -6406,6 +7772,7 @@
},
{
"BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
"PerPkg": "1",
@@ -6415,6 +7782,7 @@
},
{
"BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
"PerPkg": "1",
@@ -6424,6 +7792,7 @@
},
{
"BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
"PerPkg": "1",
@@ -6433,6 +7802,7 @@
},
{
"BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
"PerPkg": "1",
@@ -6442,8 +7812,10 @@
},
{
"BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc57fe01",
@@ -6451,8 +7823,10 @@
},
{
"BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc877de01",
@@ -6460,8 +7834,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86ffe01",
@@ -6469,8 +7845,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc867fe01",
@@ -6478,8 +7856,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8678601",
@@ -6487,8 +7867,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8678a01",
@@ -6496,8 +7878,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f8601",
@@ -6505,8 +7889,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f8a01",
@@ -6514,8 +7900,10 @@
},
{
"BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc87fde01",
@@ -6523,6 +7911,7 @@
},
{
"BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
"PerPkg": "1",
@@ -6532,6 +7921,7 @@
},
{
"BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
"PerPkg": "1",
@@ -6541,6 +7931,7 @@
},
{
"BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
"PerPkg": "1",
@@ -6550,8 +7941,10 @@
},
{
"BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc3fff01",
@@ -6559,8 +7952,10 @@
},
{
"BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc37ff01",
@@ -6568,8 +7963,10 @@
},
{
"BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc2fff01",
@@ -6577,8 +7974,10 @@
},
{
"BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc27ff01",
@@ -6586,8 +7985,10 @@
},
{
"BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc67ff01",
@@ -6595,8 +7996,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86fff01",
@@ -6604,8 +8007,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc867ff01",
@@ -6613,6 +8018,7 @@
},
{
"BriefDescription": "TOR Inserts : All requests from IO Devices",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO",
"PerPkg": "1",
@@ -6622,8 +8028,10 @@
},
{
"BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8c3ff04",
@@ -6631,6 +8039,7 @@
},
{
"BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
"PerPkg": "1",
@@ -6640,6 +8049,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
"PerPkg": "1",
@@ -6649,6 +8059,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
@@ -6658,6 +8069,7 @@
},
{
"BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
"PerPkg": "1",
@@ -6667,8 +8079,10 @@
},
{
"BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc803fd04",
@@ -6676,6 +8090,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
"PerPkg": "1",
@@ -6685,6 +8100,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
"PerPkg": "1",
@@ -6694,6 +8110,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
"PerPkg": "1",
@@ -6703,6 +8120,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
"PerPkg": "1",
@@ -6712,6 +8130,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
"PerPkg": "1",
@@ -6721,6 +8140,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
"PerPkg": "1",
@@ -6730,6 +8150,7 @@
},
{
"BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
"PerPkg": "1",
@@ -6739,6 +8160,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
"PerPkg": "1",
@@ -6748,6 +8170,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
@@ -6757,6 +8180,7 @@
},
{
"BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
"PerPkg": "1",
@@ -6766,8 +8190,10 @@
},
{
"BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc803fe04",
@@ -6775,6 +8201,7 @@
},
{
"BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
"PerPkg": "1",
@@ -6784,6 +8211,7 @@
},
{
"BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL",
"PerPkg": "1",
@@ -6793,6 +8221,7 @@
},
{
"BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE",
"PerPkg": "1",
@@ -6802,8 +8231,10 @@
},
{
"BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc803ff04",
@@ -6811,8 +8242,10 @@
},
{
"BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc23ff04",
@@ -6820,8 +8253,10 @@
},
{
"BriefDescription": "TOR Inserts : IPQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0x8",
@@ -6829,8 +8264,10 @@
},
{
"BriefDescription": "TOR Inserts : IRQ - iA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core",
"UMask": "0x1",
@@ -6838,8 +8275,10 @@
},
{
"BriefDescription": "TOR Inserts : IRQ - Non iA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0x10",
@@ -6847,24 +8286,30 @@
},
{
"BriefDescription": "TOR Inserts : Just ISOC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.ISOC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Just Local Targets",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : All from Local iA and IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
"UMask": "0xc000ff05",
@@ -6872,8 +8317,10 @@
},
{
"BriefDescription": "TOR Inserts : All from Local iA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
"UMask": "0xc000ff01",
@@ -6881,8 +8328,10 @@
},
{
"BriefDescription": "TOR Inserts : All from Local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
"UMask": "0xc000ff04",
@@ -6890,72 +8339,90 @@
},
{
"BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Just Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : MMCFG Access",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Just NearMem",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Just NonCoherent",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Just NotNearMem",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : PMM Access",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : PMM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : PRQ - IOSF",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
"UMask": "0x4",
@@ -6963,8 +8430,10 @@
},
{
"BriefDescription": "TOR Inserts : PRQ - Non IOSF",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0x20",
@@ -6972,16 +8441,20 @@
},
{
"BriefDescription": "TOR Inserts : Just Remote Targets",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : RRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.RRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0x40",
@@ -6989,8 +8462,10 @@
},
{
"BriefDescription": "TOR Inserts : WBQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.WBQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0x80",
@@ -6998,16 +8473,20 @@
},
{
"BriefDescription": "TOR Occupancy : DDR4 Access",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : SF/LLC Evictions",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
"UMask": "0x2",
@@ -7015,14 +8494,17 @@
},
{
"BriefDescription": "TOR Occupancy : Just Hits",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : All requests from iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
"PerPkg": "1",
@@ -7032,8 +8514,10 @@
},
{
"BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8c7ff01",
@@ -7041,8 +8525,10 @@
},
{
"BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8d7ff01",
@@ -7050,6 +8536,7 @@
},
{
"BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
"PerPkg": "1",
@@ -7059,8 +8546,10 @@
},
{
"BriefDescription": "TOR Occupancy; CRd Pref from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
"UMask": "0xc88fff01",
@@ -7068,6 +8557,7 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
"PerPkg": "1",
@@ -7077,8 +8567,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc837ff01",
@@ -7086,8 +8578,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc827ff01",
@@ -7095,8 +8589,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8a7ff01",
@@ -7104,8 +8600,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc897ff01",
@@ -7113,6 +8611,7 @@
},
{
"BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
"PerPkg": "1",
@@ -7122,8 +8621,10 @@
},
{
"BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc80ffd01",
@@ -7131,8 +8632,10 @@
},
{
"BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc88ffd01",
@@ -7140,8 +8643,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc817fd01",
@@ -7149,8 +8654,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc837fd01",
@@ -7158,8 +8665,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc827fd01",
@@ -7167,8 +8676,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8a7fd01",
@@ -7176,8 +8687,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc897fd01",
@@ -7185,8 +8698,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47fd01",
@@ -7194,8 +8709,10 @@
},
{
"BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcccffd01",
@@ -7203,8 +8720,10 @@
},
{
"BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xccd7fd01",
@@ -7212,8 +8731,10 @@
},
{
"BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xccc7fd01",
@@ -7221,8 +8742,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc807fd01",
@@ -7230,8 +8753,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc887fd01",
@@ -7239,8 +8764,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47ff01",
@@ -7248,8 +8775,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd47ff01",
@@ -7257,8 +8786,10 @@
},
{
"BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcccfff01",
@@ -7266,8 +8797,10 @@
},
{
"BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xccd7ff01",
@@ -7275,8 +8808,10 @@
},
{
"BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xccc7ff01",
@@ -7284,6 +8819,7 @@
},
{
"BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
"PerPkg": "1",
@@ -7293,6 +8829,7 @@
},
{
"BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
"PerPkg": "1",
@@ -7302,8 +8839,10 @@
},
{
"BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc80efe01",
@@ -7311,8 +8850,10 @@
},
{
"BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc88ffe01",
@@ -7320,8 +8861,10 @@
},
{
"BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc88efe01",
@@ -7329,8 +8872,10 @@
},
{
"BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc88f7e01",
@@ -7338,8 +8883,10 @@
},
{
"BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc80f7e01",
@@ -7347,6 +8894,7 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
"PerPkg": "1",
@@ -7356,8 +8904,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc837fe01",
@@ -7365,6 +8915,7 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
"PerPkg": "1",
@@ -7374,6 +8925,7 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
"PerPkg": "1",
@@ -7383,8 +8935,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8168601",
@@ -7392,8 +8946,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8168a01",
@@ -7401,8 +8957,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc827fe01",
@@ -7410,8 +8968,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8a7fe01",
@@ -7419,6 +8979,7 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
"PerPkg": "1",
@@ -7428,8 +8989,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc897fe01",
@@ -7437,8 +9000,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8978601",
@@ -7446,8 +9011,10 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
"UMask": "0xc896fe01",
@@ -7455,8 +9022,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8968601",
@@ -7464,8 +9033,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8968a01",
@@ -7473,8 +9044,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8978a01",
@@ -7482,8 +9055,10 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
"UMask": "0xc8977e01",
@@ -7491,8 +9066,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8970601",
@@ -7500,8 +9077,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8970a01",
@@ -7509,6 +9088,7 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
"PerPkg": "1",
@@ -7518,8 +9098,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8170601",
@@ -7527,8 +9109,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8170a01",
@@ -7536,8 +9120,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc867fe01",
@@ -7545,8 +9131,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8678601",
@@ -7554,8 +9142,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8668601",
@@ -7563,8 +9153,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8668a01",
@@ -7572,8 +9164,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8678a01",
@@ -7581,8 +9175,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8670601",
@@ -7590,8 +9186,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc8670a01",
@@ -7599,8 +9197,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47fe01",
@@ -7608,8 +9208,10 @@
},
{
"BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcccffe01",
@@ -7617,8 +9219,10 @@
},
{
"BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xccd7fe01",
@@ -7626,8 +9230,10 @@
},
{
"BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xccc7fe01",
@@ -7635,8 +9241,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8668601",
@@ -7644,8 +9252,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8668a01",
@@ -7653,8 +9263,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86e8601",
@@ -7662,8 +9274,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86e8a01",
@@ -7671,8 +9285,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86ffe01",
@@ -7680,8 +9296,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86f8601",
@@ -7689,8 +9307,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86e8601",
@@ -7698,8 +9318,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86e8a01",
@@ -7707,8 +9329,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86f8a01",
@@ -7716,8 +9340,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86f0601",
@@ -7725,8 +9351,10 @@
},
{
"BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
"UMask": "0xc86f0a01",
@@ -7734,8 +9362,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8670601",
@@ -7743,8 +9373,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8670a01",
@@ -7752,8 +9384,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f0601",
@@ -7761,8 +9395,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f0a01",
@@ -7770,6 +9406,7 @@
},
{
"BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
"PerPkg": "1",
@@ -7779,8 +9416,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc806fe01",
@@ -7788,8 +9427,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc887fe01",
@@ -7797,8 +9438,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc886fe01",
@@ -7806,8 +9449,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8877e01",
@@ -7815,8 +9460,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8077e01",
@@ -7824,8 +9471,10 @@
},
{
"BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC: For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc57fe01",
@@ -7833,8 +9482,10 @@
},
{
"BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc877de01",
@@ -7842,8 +9493,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86ffe01",
@@ -7851,8 +9504,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc867fe01",
@@ -7860,8 +9515,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8678601",
@@ -7869,8 +9526,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8678a01",
@@ -7878,8 +9537,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f8601",
@@ -7887,8 +9548,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f8a01",
@@ -7896,8 +9559,10 @@
},
{
"BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc87fde01",
@@ -7905,6 +9570,7 @@
},
{
"BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
"PerPkg": "1",
@@ -7914,8 +9580,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc887ff01",
@@ -7923,8 +9591,10 @@
},
{
"BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc57ff01",
@@ -7932,8 +9602,10 @@
},
{
"BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc27ff01",
@@ -7941,8 +9613,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86fff01",
@@ -7950,8 +9624,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc867ff01",
@@ -7959,6 +9635,7 @@
},
{
"BriefDescription": "TOR Occupancy : All requests from IO Devices",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
"PerPkg": "1",
@@ -7968,8 +9645,10 @@
},
{
"BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8c3ff04",
@@ -7977,6 +9656,7 @@
},
{
"BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
"PerPkg": "1",
@@ -7986,8 +9666,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc43fd04",
@@ -7995,8 +9677,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd43fd04",
@@ -8004,8 +9688,10 @@
},
{
"BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8f3fd04",
@@ -8013,8 +9699,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc803fd04",
@@ -8022,8 +9710,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc43ff04",
@@ -8031,8 +9721,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd43ff04",
@@ -8040,6 +9732,7 @@
},
{
"BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
"PerPkg": "1",
@@ -8049,8 +9742,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc43fe04",
@@ -8058,8 +9753,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd43fe04",
@@ -8067,6 +9764,7 @@
},
{
"BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
"PerPkg": "1",
@@ -8076,8 +9774,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc803fe04",
@@ -8085,6 +9785,7 @@
},
{
"BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
"PerPkg": "1",
@@ -8094,8 +9795,10 @@
},
{
"BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc803ff04",
@@ -8103,8 +9806,10 @@
},
{
"BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc23ff04",
@@ -8112,8 +9817,10 @@
},
{
"BriefDescription": "TOR Occupancy : IPQ",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0x8",
@@ -8121,8 +9828,10 @@
},
{
"BriefDescription": "TOR Occupancy : IRQ - iA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core",
"UMask": "0x1",
@@ -8130,8 +9839,10 @@
},
{
"BriefDescription": "TOR Occupancy : IRQ - Non iA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0x10",
@@ -8139,24 +9850,30 @@
},
{
"BriefDescription": "TOR Occupancy : Just ISOC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Just Local Targets",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : All from Local iA and IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
"UMask": "0xc000ff05",
@@ -8164,8 +9881,10 @@
},
{
"BriefDescription": "TOR Occupancy : All from Local iA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
"UMask": "0xc000ff01",
@@ -8173,8 +9892,10 @@
},
{
"BriefDescription": "TOR Occupancy : All from Local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
"UMask": "0xc000ff04",
@@ -8182,72 +9903,90 @@
},
{
"BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Just Misses",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : MMCFG Access",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Just NearMem",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Just NonCoherent",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Just NotNearMem",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : PMM Access",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : PRQ - IOSF",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
"UMask": "0x4",
@@ -8255,8 +9994,10 @@
},
{
"BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0x20",
@@ -8264,16 +10005,20 @@
},
{
"BriefDescription": "TOR Occupancy : Just Remote Targets",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8281,8 +10026,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -8290,8 +10037,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -8299,8 +10048,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8308,8 +10059,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -8317,8 +10070,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -8326,8 +10081,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8335,8 +10092,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -8344,8 +10103,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -8353,8 +10114,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -8362,8 +10125,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x80",
@@ -8371,8 +10136,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8380,8 +10147,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -8389,8 +10158,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -8398,8 +10169,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
@@ -8407,8 +10180,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8416,8 +10191,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -8425,8 +10202,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -8434,8 +10213,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -8443,8 +10224,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -8452,8 +10235,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8461,8 +10246,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -8470,8 +10257,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -8479,8 +10268,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -8488,8 +10279,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8497,8 +10290,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -8506,8 +10301,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -8515,8 +10312,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -8524,8 +10323,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -8533,8 +10334,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8542,8 +10345,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -8551,8 +10356,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -8560,8 +10367,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -8569,8 +10378,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8578,8 +10389,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -8587,8 +10400,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -8596,8 +10411,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -8605,8 +10422,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -8614,8 +10433,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8623,8 +10444,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -8632,8 +10455,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -8641,8 +10466,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -8650,8 +10477,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8659,8 +10488,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x10",
@@ -8668,8 +10499,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x1",
@@ -8677,8 +10510,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x2",
@@ -8686,8 +10521,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x80",
@@ -8695,8 +10532,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8704,8 +10543,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x40",
@@ -8713,8 +10554,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x4",
@@ -8722,8 +10565,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x8",
@@ -8731,8 +10576,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8740,8 +10587,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -8749,8 +10598,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -8758,8 +10609,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -8767,8 +10620,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -8776,8 +10631,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8785,8 +10642,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -8794,8 +10653,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -8803,8 +10664,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -8812,8 +10675,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x1",
@@ -8821,8 +10686,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x1",
@@ -8830,8 +10697,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_CHA_TxR_HORZ_STARVED.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x2",
@@ -8839,8 +10708,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x80",
@@ -8848,8 +10719,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x4",
@@ -8857,8 +10730,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x4",
@@ -8866,8 +10741,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x8",
@@ -8875,8 +10752,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -8884,8 +10763,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -8893,8 +10774,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -8902,8 +10785,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -8911,8 +10796,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -8920,8 +10807,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -8929,8 +10818,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -8938,8 +10829,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x20",
@@ -8947,8 +10840,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -8956,8 +10851,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -8965,8 +10862,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
@@ -8974,8 +10873,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -8983,8 +10884,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -8992,8 +10895,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -9001,8 +10906,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -9010,8 +10917,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -9019,8 +10928,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -9028,8 +10939,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -9037,8 +10950,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -9046,8 +10961,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -9055,8 +10972,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -9064,8 +10983,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -9073,8 +10994,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -9082,8 +11005,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -9091,8 +11016,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -9100,8 +11027,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -9109,8 +11038,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -9118,8 +11049,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -9127,8 +11060,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -9136,8 +11071,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -9145,8 +11082,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -9154,8 +11093,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -9163,8 +11104,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -9172,8 +11115,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -9181,8 +11126,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -9190,8 +11137,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -9199,8 +11148,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -9208,8 +11159,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -9217,8 +11170,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -9226,8 +11181,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -9235,8 +11192,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
@@ -9244,8 +11203,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x10",
@@ -9253,8 +11214,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
@@ -9262,8 +11225,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
@@ -9271,8 +11236,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x4",
@@ -9280,8 +11247,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x40",
@@ -9289,8 +11258,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x8",
@@ -9298,8 +11269,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
@@ -9307,8 +11280,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
@@ -9316,8 +11291,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -9325,8 +11302,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -9334,8 +11313,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -9343,8 +11324,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -9352,8 +11335,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -9361,8 +11346,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -9370,8 +11357,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -9379,8 +11368,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -9388,8 +11379,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -9397,8 +11390,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
@@ -9406,8 +11401,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x10",
@@ -9415,8 +11412,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
@@ -9424,8 +11423,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x20",
@@ -9433,8 +11434,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
@@ -9442,8 +11445,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x40",
@@ -9451,8 +11456,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x8",
@@ -9460,8 +11467,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
@@ -9469,8 +11478,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
@@ -9478,8 +11489,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
@@ -9487,8 +11500,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -9496,8 +11511,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -9505,8 +11522,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -9514,8 +11533,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -9523,8 +11544,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -9532,8 +11555,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -9541,8 +11566,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -9550,8 +11577,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -9559,8 +11588,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -9568,8 +11599,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -9577,8 +11610,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -9586,8 +11621,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -9595,8 +11632,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -9604,8 +11643,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -9613,8 +11654,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -9622,8 +11665,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -9631,8 +11676,10 @@
},
{
"BriefDescription": "Vertical IV Ring in Use : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
@@ -9640,8 +11687,10 @@
},
{
"BriefDescription": "Vertical IV Ring in Use : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
@@ -9649,8 +11698,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -9658,8 +11709,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -9667,8 +11720,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -9676,8 +11731,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -9685,8 +11742,10 @@
},
{
"BriefDescription": "WbPushMtoI : Pushed to LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC",
"UMask": "0x1",
@@ -9694,8 +11753,10 @@
},
{
"BriefDescription": "WbPushMtoI : Pushed to Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
"UMask": "0x2",
@@ -9703,8 +11764,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.",
"UMask": "0x1",
@@ -9712,8 +11775,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.",
"UMask": "0x2",
@@ -9721,40 +11786,50 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only.",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only.",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only.",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only.",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.",
"UMask": "0x4",
@@ -9762,8 +11837,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.",
"UMask": "0x8",
@@ -9771,8 +11848,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.",
"UMask": "0x10",
@@ -9780,8 +11859,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.",
"UMask": "0x20",
@@ -9789,8 +11870,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only.",
"UMask": "0x40",
@@ -9798,8 +11881,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only.",
"UMask": "0x80",
@@ -9807,24 +11892,30 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only.",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only.",
"Unit": "CHA"
},
{
"BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
"UMask": "0x8",
@@ -9832,8 +11923,10 @@
},
{
"BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
"UMask": "0x4",
@@ -9841,8 +11934,10 @@
},
{
"BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
"UMask": "0x80",
@@ -9850,8 +11945,10 @@
},
{
"BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
"UMask": "0x40",
@@ -9859,8 +11956,10 @@
},
{
"BriefDescription": "XPT Prefetches : Sent (on 0?)",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.SENT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent",
"UMask": "0x1",
@@ -9868,8 +11967,10 @@
},
{
"BriefDescription": "XPT Prefetches : Sent (on 1?)",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.SENT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent",
"UMask": "0x10",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json
index 6997e6f7d366..97bec6cfc79c 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json
@@ -1,8 +1,10 @@
[
{
"BriefDescription": "Total Write Cache Occupancy : Any Source",
+ "Counter": "0,1",
"EventCode": "0x0F",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.",
"UMask": "0x1",
@@ -10,8 +12,10 @@
},
{
"BriefDescription": "Total Write Cache Occupancy : Snoops",
+ "Counter": "0,1",
"EventCode": "0x0F",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
"UMask": "0x2",
@@ -19,6 +23,7 @@
},
{
"BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
+ "Counter": "0,1",
"EventCode": "0x0f",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
"PerPkg": "1",
@@ -28,6 +33,7 @@
},
{
"BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
+ "Counter": "0,1",
"EventCode": "0x01",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
@@ -35,8 +41,10 @@
},
{
"BriefDescription": "Coherent Ops : CLFlush",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations serviced by the IRP",
"UMask": "0x80",
@@ -44,6 +52,7 @@
},
{
"BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
@@ -53,8 +62,10 @@
},
{
"BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
"UMask": "0x8",
@@ -62,6 +73,7 @@
},
{
"BriefDescription": "Coherent Ops : WbMtoI",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
@@ -71,6 +83,7 @@
},
{
"BriefDescription": "FAF RF full",
+ "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_FAF_FULL",
"PerPkg": "1",
@@ -78,6 +91,7 @@
},
{
"BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
+ "Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_FAF_INSERTS",
"PerPkg": "1",
@@ -86,6 +100,7 @@
},
{
"BriefDescription": "Occupancy of the IRP FAF queue.",
+ "Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_FAF_OCCUPANCY",
"PerPkg": "1",
@@ -94,6 +109,7 @@
},
{
"BriefDescription": "FAF allocation -- sent to ADQ",
+ "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_FAF_TRANSACTIONS",
"PerPkg": "1",
@@ -101,14 +117,17 @@
},
{
"BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+ "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_I_IRP_ALL.EVICTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
+ "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
"PerPkg": "1",
@@ -117,78 +136,97 @@
},
{
"BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+ "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
+ "Counter": "0,1",
"EventCode": "0x1E",
"EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
+ "Counter": "0,1",
"EventCode": "0x1E",
"EventName": "UNC_I_MISC0.FAST_REJ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.FAST_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers >From Primary to Secondary",
+ "Counter": "0,1",
"EventCode": "0x1E",
"EventName": "UNC_I_MISC0.FAST_XFER",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints >From Primary to Secondary",
+ "Counter": "0,1",
"EventCode": "0x1E",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
+ "Counter": "0,1",
"EventCode": "0x1E",
"EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1 : Lost Forward",
+ "Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
@@ -198,8 +236,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Received Invalid",
+ "Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state",
"UMask": "0x20",
@@ -207,8 +247,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Received Valid",
+ "Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state",
"UMask": "0x40",
@@ -216,8 +258,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state",
"UMask": "0x4",
@@ -225,8 +269,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_I",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.",
"UMask": "0x1",
@@ -234,8 +280,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_M",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.",
"UMask": "0x8",
@@ -243,8 +291,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state",
"UMask": "0x2",
@@ -252,88 +302,110 @@
},
{
"BriefDescription": "P2P Requests",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_P2P_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "P2P Requests : P2P requests from the ITC",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Occupancy",
+ "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_P2P_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : P2P completions",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : match if local only",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : match if local and target matches",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : P2P Message",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : P2P reads",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : Match if remote only",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : match if remote and target matches",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : P2P Writes",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
"UMask": "0x7e",
@@ -341,8 +413,10 @@
},
{
"BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
"UMask": "0x74",
@@ -350,8 +424,10 @@
},
{
"BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
"UMask": "0x72",
@@ -359,6 +435,7 @@
},
{
"BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
"PerPkg": "1",
@@ -368,8 +445,10 @@
},
{
"BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
"UMask": "0x71",
@@ -377,64 +456,80 @@
},
{
"BriefDescription": "Snoop Responses : Hit E or S",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : Hit I",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : Hit M",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : Miss",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.MISS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : SnpCode",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : SnpData",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : SnpInv",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count : Atomic",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions",
"UMask": "0x10",
@@ -442,8 +537,10 @@
},
{
"BriefDescription": "Inbound Transaction Count : Other",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_TRANSACTIONS.OTHER",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.",
"UMask": "0x20",
@@ -451,8 +548,10 @@
},
{
"BriefDescription": "Inbound Transaction Count : Writes",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
"UMask": "0x2",
@@ -460,6 +559,7 @@
},
{
"BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
@@ -469,134 +569,170 @@
},
{
"BriefDescription": "AK Egress Allocations",
+ "Counter": "0,1",
"EventCode": "0x0B",
"EventName": "UNC_I_TxC_AK_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL DRS Egress Cycles Full",
+ "Counter": "0,1",
"EventCode": "0x05",
"EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL DRS Egress Inserts",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL DRS Egress Occupancy",
+ "Counter": "0,1",
"EventCode": "0x08",
"EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCB Egress Cycles Full",
+ "Counter": "0,1",
"EventCode": "0x06",
"EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCB Egress Inserts",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCB Egress Occupancy",
+ "Counter": "0,1",
"EventCode": "0x09",
"EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCS Egress Cycles Full",
+ "Counter": "0,1",
"EventCode": "0x07",
"EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCS Egress Inserts",
+ "Counter": "0,1",
"EventCode": "0x04",
"EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCS Egress Occupancy",
+ "Counter": "0,1",
"EventCode": "0x0A",
"EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+ "Counter": "0,1",
"EventCode": "0x1C",
"EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2",
"Unit": "IRP"
},
{
"BriefDescription": "No AD0 Egress Credits Stalls",
+ "Counter": "0,1",
"EventCode": "0x1A",
"EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "No AD1 Egress Credits Stalls",
+ "Counter": "0,1",
"EventCode": "0x1B",
"EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "No BL Egress Credit Stalls",
+ "Counter": "0,1",
"EventCode": "0x1D",
"EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
+ "Counter": "0,1",
"EventCode": "0x0D",
"EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
+ "Counter": "0,1",
"EventCode": "0x0E",
"EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
+ "Counter": "0,1",
"EventCode": "0x0C",
"EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.",
"Unit": "IRP"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -604,8 +740,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -613,8 +751,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -622,8 +762,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -631,8 +773,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -640,8 +784,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -649,8 +795,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -658,8 +806,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -667,8 +817,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -676,8 +828,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -685,8 +839,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -694,8 +850,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -703,8 +861,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -712,8 +872,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -721,8 +883,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -730,8 +894,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -739,8 +905,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -748,8 +916,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -757,8 +927,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -766,8 +938,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -775,8 +949,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -784,8 +960,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -793,8 +971,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -802,8 +982,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -811,8 +993,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -820,8 +1004,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -829,8 +1015,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -838,8 +1026,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -847,8 +1037,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -856,8 +1048,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -865,8 +1059,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -874,8 +1070,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -883,8 +1081,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -892,8 +1092,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -901,8 +1103,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -910,8 +1114,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -919,8 +1125,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -928,8 +1136,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -937,8 +1147,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -946,8 +1158,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -955,8 +1169,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -964,8 +1180,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -973,8 +1191,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -982,8 +1202,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -991,8 +1213,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -1000,8 +1224,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -1009,8 +1235,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -1018,8 +1246,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -1027,8 +1257,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -1036,8 +1268,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -1045,8 +1279,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -1054,8 +1290,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -1063,8 +1301,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -1072,8 +1312,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -1081,8 +1323,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -1090,8 +1334,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -1099,8 +1345,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -1108,8 +1356,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -1117,8 +1367,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -1126,8 +1378,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -1135,8 +1389,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -1144,8 +1400,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -1153,8 +1411,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -1162,8 +1422,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -1171,8 +1433,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -1180,8 +1444,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -1189,8 +1455,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -1198,8 +1466,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -1207,8 +1477,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -1216,8 +1488,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -1225,8 +1499,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -1234,8 +1510,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -1243,8 +1521,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -1252,8 +1532,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -1261,8 +1543,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -1270,8 +1554,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -1279,8 +1565,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -1288,8 +1576,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -1297,8 +1587,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -1306,8 +1598,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -1315,8 +1609,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -1324,8 +1620,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -1333,8 +1631,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -1342,8 +1642,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -1351,8 +1653,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -1360,8 +1664,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -1369,8 +1675,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -1378,8 +1686,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -1387,44 +1697,54 @@
},
{
"BriefDescription": "M2M to iMC Bypass : Not Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC Bypass : Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC Bypass : Not Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC Bypass : Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Clockticks of the mesh to memory (M2M)",
+ "Counter": "0,1,2,3",
"EventName": "UNC_M2M_CLOCKTICKS",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M2M_CMS_CLOCKTICKS",
"PerPkg": "1",
@@ -1432,113 +1752,142 @@
},
{
"BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number of reads in which direct to core transaction was overridden",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles when Direct2UPI was Disabled",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Clockticks of the mesh to PCI (M2P)",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
"PerPkg": "1",
@@ -1547,6 +1896,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
"PerPkg": "1",
@@ -1555,6 +1905,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
"PerPkg": "1",
@@ -1563,6 +1914,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
"PerPkg": "1",
@@ -1571,70 +1923,87 @@
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
@@ -1643,8 +2012,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Local",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
"UMask": "0x4",
@@ -1652,8 +2023,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
"UMask": "0x8",
@@ -1661,8 +2034,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
"UMask": "0x40",
@@ -1670,8 +2045,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
@@ -1679,8 +2056,10 @@
},
{
"BriefDescription": "Distress signal asserted : Horizontal",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x2",
@@ -1688,8 +2067,10 @@
},
{
"BriefDescription": "Distress signal asserted : PMM Local",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x10",
@@ -1697,8 +2078,10 @@
},
{
"BriefDescription": "Distress signal asserted : PMM Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x20",
@@ -1706,8 +2089,10 @@
},
{
"BriefDescription": "Distress signal asserted : Vertical",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x1",
@@ -1715,22 +2100,28 @@
},
{
"BriefDescription": "UNC_M2M_DISTRESS_PMM",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "UNC_M2M_DISTRESS_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x4",
@@ -1738,8 +2129,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x1",
@@ -1747,8 +2140,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -1756,8 +2151,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -1765,8 +2162,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -1774,8 +2173,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -1783,8 +2184,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -1792,8 +2195,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -1801,8 +2206,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -1810,8 +2217,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -1819,8 +2228,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -1828,8 +2239,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -1837,8 +2250,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -1846,8 +2261,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -1855,8 +2272,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -1864,8 +2283,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -1873,8 +2294,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -1882,8 +2305,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -1891,8 +2316,10 @@
},
{
"BriefDescription": "Horizontal IV Ring in Use : Left",
+ "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
@@ -1900,8 +2327,10 @@
},
{
"BriefDescription": "Horizontal IV Ring in Use : Right",
+ "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
@@ -1909,64 +2338,80 @@
},
{
"BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x704",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x104",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x140",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x102",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x101",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x110",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x108",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2M Reads Issued to iMC : PMM - Ch0 : Counts all PMM dimm read requests(full line) sent from M2M to iMC",
"UMask": "0x120",
@@ -1974,56 +2419,70 @@
},
{
"BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x204",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x240",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x202",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x201",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x210",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x208",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2M Reads Issued to iMC : PMM - Ch1 : Counts all PMM dimm read requests(full line) sent from M2M to iMC",
"UMask": "0x220",
@@ -2031,54 +2490,67 @@
},
{
"BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x440",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x740",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x702",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.NORMAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x701",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x710",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x708",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.TO_PMM",
"PerPkg": "1",
@@ -2087,93 +2559,117 @@
},
{
"BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c10",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x410",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x401",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x404",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_NI",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x402",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x408",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x440",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x420",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2M Writes Issued to iMC : PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC",
"UMask": "0x480",
@@ -2181,85 +2677,107 @@
},
{
"BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x810",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x801",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x804",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_NI",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x802",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x808",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x840",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x820",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2M Writes Issued to iMC : PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC",
"UMask": "0x880",
@@ -2267,75 +2785,94 @@
},
{
"BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.FULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c01",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c04",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.NI",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c02",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c08",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c40",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c20",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
"PerPkg": "1",
@@ -2344,281 +2881,353 @@
},
{
"BriefDescription": "Write Tracker Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Number Packet Header Matches : MC Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M2M_PKT_MATCH.MC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Number Packet Header Matches : Mesh Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M2M_PKT_MATCH.MESH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
+ "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Full : All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Full : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
+ "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : UPI - Ch 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : UPI - Ch 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : UPI - Ch 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : XPT - Ch 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : UPI - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2a",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x15",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0",
"UMask": "0x1",
@@ -2626,8 +3235,10 @@
},
{
"BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1",
"UMask": "0x4",
@@ -2635,8 +3246,10 @@
},
{
"BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2",
"UMask": "0x10",
@@ -2644,8 +3257,10 @@
},
{
"BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels",
"UMask": "0x15",
@@ -2653,8 +3268,10 @@
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0",
"UMask": "0x1",
@@ -2662,8 +3279,10 @@
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1",
"UMask": "0x4",
@@ -2671,460 +3290,578 @@
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x15",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x6d",
"EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2a",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x15",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Occupancy : All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Occupancy : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": ": All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": ": Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": ": Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": ": Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "Counter": "0,1,2,3",
"EventCode": "0x7A",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+ "Counter": "0,1,2,3",
"EventCode": "0x7A",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+ "Counter": "0,1,2,3",
"EventCode": "0x7A",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "Counter": "0,1,2,3",
"EventCode": "0x7A",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
+ "Counter": "0,1,2,3",
"EventCode": "0x78",
"EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+ "Counter": "0,1,2,3",
"EventCode": "0x77",
"EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x1",
@@ -3132,8 +3869,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x2",
@@ -3141,8 +3880,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x4",
@@ -3150,8 +3891,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x8",
@@ -3159,8 +3902,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x1",
@@ -3168,8 +3913,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x2",
@@ -3177,8 +3924,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x10",
@@ -3186,8 +3935,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x4",
@@ -3195,8 +3946,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x8",
@@ -3204,237 +3957,299 @@
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Source Throttle",
+ "Counter": "0,1,2,3",
"EventCode": "0xae",
"EventName": "UNC_M2M_RING_SRC_THRTL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M2M_RxC_AD_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x77",
"EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M2M_RxC_AK_WR_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Ingress (from CMS) Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Ingress (from CMS) Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x07",
"EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Ingress (from CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M2M_RxC_BL_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Ingress (from CMS) Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x11",
@@ -3442,8 +4257,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
@@ -3451,8 +4268,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x1",
@@ -3460,8 +4279,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x44",
@@ -3469,8 +4290,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
@@ -3478,8 +4301,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x4",
@@ -3487,8 +4312,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
@@ -3496,8 +4323,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x10",
@@ -3505,8 +4334,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x1",
@@ -3514,8 +4345,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
"UMask": "0x2",
@@ -3523,8 +4356,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x80",
@@ -3532,8 +4367,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x44",
@@ -3541,8 +4378,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x40",
@@ -3550,8 +4389,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x4",
@@ -3559,8 +4400,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
"UMask": "0x8",
@@ -3568,8 +4411,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -3577,8 +4422,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x10",
@@ -3586,8 +4433,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x1",
@@ -3595,8 +4444,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x2",
@@ -3604,8 +4455,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -3613,8 +4466,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x40",
@@ -3622,8 +4477,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x4",
@@ -3631,8 +4488,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x80",
@@ -3640,8 +4499,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x8",
@@ -3649,16 +4510,20 @@
},
{
"BriefDescription": "Transgress Injection Starvation",
+ "Counter": "0,1,2,3",
"EventCode": "0xe4",
"EventName": "UNC_M2M_RxR_CRD_STARVED_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
@@ -3666,8 +4531,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
@@ -3675,8 +4542,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
@@ -3684,8 +4553,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
@@ -3693,8 +4564,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
@@ -3702,8 +4575,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
@@ -3711,8 +4586,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x40",
@@ -3720,8 +4597,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
@@ -3729,8 +4608,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
@@ -3738,8 +4619,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
@@ -3747,8 +4630,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
@@ -3756,8 +4641,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
@@ -3765,8 +4652,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
@@ -3774,8 +4663,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
@@ -3783,8 +4674,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
@@ -3792,8 +4685,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
@@ -3801,8 +4696,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
@@ -3810,8 +4707,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
@@ -3819,64 +4718,82 @@
},
{
"BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Retry - Mem Mirroring Mode",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Retry - Mem Mirroring Mode",
+ "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Scoreboard Accepts",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Scoreboard Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Scoreboard Accepts",
+ "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Scoreboard Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -3884,8 +4801,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -3893,8 +4812,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -3902,8 +4823,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -3911,8 +4834,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -3920,8 +4845,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -3929,8 +4856,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -3938,8 +4867,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -3947,8 +4878,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -3956,8 +4889,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -3965,8 +4900,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -3974,8 +4911,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -3983,8 +4922,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -3992,8 +4933,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -4001,8 +4944,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -4010,8 +4955,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -4019,8 +4966,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -4028,8 +4977,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -4037,8 +4988,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -4046,8 +4999,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -4055,8 +5010,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -4064,8 +5021,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -4073,8 +5032,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -4082,8 +5043,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -4091,8 +5054,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -4100,8 +5065,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -4109,8 +5076,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -4118,8 +5087,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -4127,8 +5098,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -4136,8 +5109,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -4145,8 +5120,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -4154,8 +5131,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -4163,8 +5142,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -4172,8 +5153,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -4181,8 +5164,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -4190,8 +5175,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -4199,8 +5186,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -4208,8 +5197,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -4217,8 +5208,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -4226,8 +5219,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -4235,8 +5230,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -4244,8 +5241,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -4253,8 +5252,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -4262,8 +5263,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -4271,6 +5274,7 @@
},
{
"BriefDescription": "Tag Hit : Clean NearMem Read Hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
"PerPkg": "1",
@@ -4280,6 +5284,7 @@
},
{
"BriefDescription": "Tag Hit : Dirty NearMem Read Hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
"PerPkg": "1",
@@ -4289,8 +5294,10 @@
},
{
"BriefDescription": "Tag Hit : Clean NearMem Underfill Hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tag Hit : Clean NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write",
"UMask": "0x4",
@@ -4298,8 +5305,10 @@
},
{
"BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tag Hit : Dirty NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write",
"UMask": "0x8",
@@ -4307,620 +5316,778 @@
},
{
"BriefDescription": "Tag Miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M2M_TAG_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number AD Ingress Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M2M_TGR_AD_CREDITS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number BL Ingress Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2M_TGR_BL_CREDITS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Full : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2M_TRACKER_FULL.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Full : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2M_TRACKER_FULL.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Full : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2M_TRACKER_FULL.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Inserts : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Not Empty : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2M_TRACKER_NE.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Not Empty : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2M_TRACKER_NE.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Not Empty : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2M_TRACKER_NE.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Occupancy : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Credit Acquired",
+ "Counter": "0,1,2,3",
"EventCode": "0x0d",
"EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Credits Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x0e",
"EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x0c",
"EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x0b",
"EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x09",
"EventName": "UNC_M2M_TxC_AD_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x0f",
"EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x0A",
"EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_M2M_TxC_AK.NDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AKC Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M2M_TxC_AKC_CREDITS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x88",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa0",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x90",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2M_TxC_BL.DRS_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Full : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Not Empty : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Allocations : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -4928,8 +6095,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -4937,8 +6106,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -4946,8 +6117,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -4955,8 +6128,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -4964,8 +6139,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -4973,8 +6150,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -4982,8 +6161,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -4991,8 +6172,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -5000,8 +6183,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -5009,8 +6194,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x80",
@@ -5018,8 +6205,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -5027,8 +6216,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -5036,8 +6227,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -5045,8 +6238,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
@@ -5054,8 +6249,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -5063,8 +6260,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -5072,8 +6271,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -5081,8 +6282,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -5090,8 +6293,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -5099,8 +6304,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -5108,8 +6315,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -5117,8 +6326,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -5126,8 +6337,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -5135,8 +6348,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -5144,8 +6359,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -5153,8 +6370,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -5162,8 +6381,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -5171,8 +6392,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -5180,8 +6403,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -5189,8 +6414,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -5198,8 +6425,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -5207,8 +6436,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -5216,8 +6447,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -5225,8 +6458,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -5234,8 +6469,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -5243,8 +6480,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -5252,8 +6491,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -5261,8 +6502,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -5270,8 +6513,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -5279,8 +6524,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -5288,8 +6535,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -5297,8 +6546,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x11",
@@ -5306,8 +6557,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x10",
@@ -5315,8 +6568,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x1",
@@ -5324,8 +6579,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x2",
@@ -5333,8 +6590,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x80",
@@ -5342,8 +6601,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x44",
@@ -5351,8 +6612,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x40",
@@ -5360,8 +6623,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x4",
@@ -5369,8 +6634,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x8",
@@ -5378,8 +6645,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -5387,8 +6656,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -5396,8 +6667,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -5405,8 +6678,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -5414,8 +6689,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -5423,8 +6700,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -5432,8 +6711,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -5441,8 +6722,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -5450,8 +6733,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -5459,8 +6744,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x1",
@@ -5468,8 +6755,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x1",
@@ -5477,8 +6766,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x2",
@@ -5486,8 +6777,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x80",
@@ -5495,8 +6788,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x4",
@@ -5504,8 +6799,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x4",
@@ -5513,8 +6810,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x8",
@@ -5522,8 +6821,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -5531,8 +6832,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -5540,8 +6843,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -5549,8 +6854,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -5558,8 +6865,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -5567,8 +6876,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -5576,8 +6887,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -5585,8 +6898,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x20",
@@ -5594,8 +6909,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -5603,8 +6920,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -5612,8 +6931,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
@@ -5621,8 +6942,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -5630,8 +6953,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -5639,8 +6964,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -5648,8 +6975,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -5657,8 +6986,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -5666,8 +6997,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -5675,8 +7008,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -5684,8 +7019,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -5693,8 +7030,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -5702,8 +7041,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -5711,8 +7052,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -5720,8 +7063,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -5729,8 +7074,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -5738,8 +7085,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -5747,8 +7096,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -5756,8 +7107,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -5765,8 +7118,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -5774,8 +7129,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -5783,8 +7140,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -5792,8 +7151,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -5801,8 +7162,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -5810,8 +7173,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -5819,8 +7184,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -5828,8 +7195,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -5837,8 +7206,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -5846,8 +7217,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -5855,8 +7228,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -5864,8 +7239,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -5873,8 +7250,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -5882,8 +7261,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
@@ -5891,8 +7272,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x10",
@@ -5900,8 +7283,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
@@ -5909,8 +7294,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
@@ -5918,8 +7305,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x4",
@@ -5927,8 +7316,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x40",
@@ -5936,8 +7327,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x8",
@@ -5945,8 +7338,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
@@ -5954,8 +7349,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
@@ -5963,8 +7360,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -5972,8 +7371,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -5981,8 +7382,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -5990,8 +7393,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -5999,8 +7404,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -6008,8 +7415,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -6017,8 +7426,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -6026,8 +7437,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -6035,8 +7448,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -6044,8 +7459,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
@@ -6053,8 +7470,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x10",
@@ -6062,8 +7481,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
@@ -6071,8 +7492,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x20",
@@ -6080,8 +7503,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
@@ -6089,8 +7514,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x40",
@@ -6098,8 +7525,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x8",
@@ -6107,8 +7536,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
@@ -6116,8 +7547,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
@@ -6125,8 +7558,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
@@ -6134,8 +7569,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -6143,8 +7580,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -6152,8 +7591,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -6161,8 +7602,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -6170,8 +7613,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -6179,8 +7624,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -6188,8 +7635,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -6197,8 +7646,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -6206,8 +7657,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -6215,8 +7668,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -6224,8 +7679,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -6233,8 +7690,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -6242,8 +7701,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -6251,8 +7712,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -6260,8 +7723,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -6269,8 +7734,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -6278,8 +7745,10 @@
},
{
"BriefDescription": "Vertical IV Ring in Use : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
@@ -6287,8 +7756,10 @@
},
{
"BriefDescription": "Vertical IV Ring in Use : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
@@ -6296,8 +7767,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -6305,8 +7778,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -6314,8 +7789,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -6323,8 +7800,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -6332,352 +7811,440 @@
},
{
"BriefDescription": "WPQ Flush : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_WPQ_FLUSH.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "WPQ Flush : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_WPQ_FLUSH.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "WPQ Flush : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_WPQ_FLUSH.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Full : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Full : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Full : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M2M_WR_TRACKER_FULL.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Full : Mirror",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Inserts : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy : Mirror",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Inserts : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Occupancy : Channel 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -6685,8 +8252,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -6694,8 +8263,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -6703,8 +8274,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -6712,8 +8285,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -6721,8 +8296,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -6730,8 +8307,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -6739,8 +8318,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -6748,8 +8329,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -6757,8 +8340,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -6766,8 +8351,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -6775,8 +8362,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -6784,8 +8373,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -6793,8 +8384,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -6802,8 +8395,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -6811,8 +8406,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -6820,8 +8417,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -6829,8 +8428,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -6838,8 +8439,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -6847,8 +8450,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -6856,8 +8461,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -6865,8 +8472,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -6874,8 +8483,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -6883,8 +8494,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -6892,8 +8505,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -6901,8 +8516,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -6910,8 +8527,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -6919,8 +8538,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -6928,8 +8549,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -6937,8 +8560,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -6946,8 +8571,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -6955,8 +8582,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -6964,8 +8593,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -6973,8 +8604,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -6982,8 +8615,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -6991,8 +8626,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -7000,8 +8637,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -7009,8 +8648,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -7018,8 +8659,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -7027,8 +8670,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -7036,8 +8681,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -7045,8 +8692,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -7054,8 +8703,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -7063,8 +8714,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -7072,8 +8725,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -7081,8 +8736,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -7090,8 +8747,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -7099,8 +8758,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -7108,8 +8769,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -7117,8 +8780,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -7126,8 +8791,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -7135,8 +8802,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -7144,8 +8813,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -7153,8 +8824,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -7162,8 +8835,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -7171,8 +8846,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -7180,8 +8857,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -7189,8 +8868,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -7198,8 +8879,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -7207,8 +8890,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -7216,8 +8901,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -7225,8 +8912,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -7234,8 +8923,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -7243,8 +8934,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -7252,8 +8945,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -7261,8 +8956,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -7270,8 +8967,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -7279,8 +8978,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -7288,8 +8989,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -7297,8 +9000,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -7306,8 +9011,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -7315,8 +9022,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -7324,8 +9033,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -7333,8 +9044,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -7342,8 +9055,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -7351,8 +9066,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -7360,8 +9077,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -7369,8 +9088,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -7378,8 +9099,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -7387,8 +9110,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -7396,8 +9121,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -7405,8 +9132,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -7414,8 +9143,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -7423,8 +9154,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -7432,8 +9165,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -7441,8 +9176,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -7450,8 +9187,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -7459,8 +9198,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -7468,8 +9209,10 @@
},
{
"BriefDescription": "CBox AD Credits Empty : Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x4",
@@ -7477,8 +9220,10 @@
},
{
"BriefDescription": "CBox AD Credits Empty : Snoops",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x8",
@@ -7486,8 +9231,10 @@
},
{
"BriefDescription": "CBox AD Credits Empty : VNA Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x1",
@@ -7495,8 +9242,10 @@
},
{
"BriefDescription": "CBox AD Credits Empty : Writebacks",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x2",
@@ -7504,6 +9253,7 @@
},
{
"BriefDescription": "Clockticks of the mesh to UPI (M3UPI)",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M3UPI_CLOCKTICKS",
"PerPkg": "1",
@@ -7512,31 +9262,39 @@
},
{
"BriefDescription": "CMS Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "D2C Sent",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M3UPI_D2C_SENT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "D2C Sent : Count cases BL sends direct to core",
"Unit": "M3UPI"
},
{
"BriefDescription": "D2U Sent",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M3UPI_D2U_SENT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Local",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
"UMask": "0x4",
@@ -7544,8 +9302,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
"UMask": "0x8",
@@ -7553,8 +9313,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
"UMask": "0x40",
@@ -7562,8 +9324,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
@@ -7571,8 +9335,10 @@
},
{
"BriefDescription": "Distress signal asserted : Horizontal",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x2",
@@ -7580,8 +9346,10 @@
},
{
"BriefDescription": "Distress signal asserted : PMM Local",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x10",
@@ -7589,8 +9357,10 @@
},
{
"BriefDescription": "Distress signal asserted : PMM Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x20",
@@ -7598,8 +9368,10 @@
},
{
"BriefDescription": "Distress signal asserted : Vertical",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x1",
@@ -7607,8 +9379,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x4",
@@ -7616,8 +9390,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x1",
@@ -7625,8 +9401,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -7634,8 +9412,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -7643,8 +9423,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -7652,8 +9434,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -7661,8 +9445,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -7670,8 +9456,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -7679,8 +9467,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -7688,8 +9478,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -7697,8 +9489,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -7706,8 +9500,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -7715,8 +9511,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -7724,8 +9522,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -7733,8 +9533,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -7742,8 +9544,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -7751,8 +9555,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -7760,8 +9566,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -7769,8 +9577,10 @@
},
{
"BriefDescription": "Horizontal IV Ring in Use : Left",
+ "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
@@ -7778,8 +9588,10 @@
},
{
"BriefDescription": "Horizontal IV Ring in Use : Right",
+ "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
@@ -7787,8 +9599,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2",
"UMask": "0x1",
@@ -7796,8 +9610,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO2",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2",
"UMask": "0x2",
@@ -7805,8 +9621,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO3",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2",
"UMask": "0x4",
@@ -7814,8 +9632,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO4",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2",
"UMask": "0x8",
@@ -7823,8 +9643,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO5",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
"UMask": "0x10",
@@ -7832,8 +9654,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2",
"UMask": "0x40",
@@ -7841,8 +9665,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2",
"UMask": "0x80",
@@ -7850,8 +9676,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO5",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
"UMask": "0x20",
@@ -7859,24 +9687,30 @@
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Multi Slot Flit Received : AD - Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x1",
@@ -7884,8 +9718,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : AD - Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x2",
@@ -7893,8 +9729,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : AD - Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x4",
@@ -7902,8 +9740,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : AK - Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x10",
@@ -7911,8 +9751,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : AK - Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x20",
@@ -7920,8 +9762,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : BL - Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x8",
@@ -7929,8 +9773,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x1",
@@ -7938,8 +9784,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x2",
@@ -7947,8 +9795,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x4",
@@ -7956,8 +9806,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x8",
@@ -7965,8 +9817,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x1",
@@ -7974,8 +9828,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x2",
@@ -7983,8 +9839,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x10",
@@ -7992,8 +9850,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x4",
@@ -8001,8 +9861,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x8",
@@ -8010,95 +9872,119 @@
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Source Throttle",
+ "Counter": "0,1,2,3",
"EventCode": "0xae",
"EventName": "UNC_M3UPI_RING_SRC_THRTL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN0 : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -8106,8 +9992,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -8115,8 +10003,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -8124,8 +10014,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -8133,8 +10025,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -8142,8 +10036,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -8151,8 +10047,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -8160,8 +10058,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -8169,8 +10069,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -8178,8 +10080,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -8187,8 +10091,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -8196,8 +10102,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -8205,8 +10113,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -8214,8 +10124,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -8223,8 +10135,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel",
"UMask": "0x10",
@@ -8232,8 +10146,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel",
"UMask": "0x20",
@@ -8241,8 +10157,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : Max Parallel Win",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners)",
"UMask": "0x80",
@@ -8250,8 +10168,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message",
"UMask": "0x1",
@@ -8259,8 +10179,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message",
"UMask": "0x2",
@@ -8268,8 +10190,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message",
"UMask": "0x4",
@@ -8277,8 +10201,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message",
"UMask": "0x8",
@@ -8286,8 +10212,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win",
+ "Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side)",
"UMask": "0x40",
@@ -8295,8 +10223,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -8304,8 +10234,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -8313,8 +10245,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -8322,8 +10256,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -8331,8 +10267,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -8340,8 +10278,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -8349,8 +10289,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -8358,8 +10300,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -8367,8 +10311,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -8376,8 +10322,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -8385,8 +10333,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -8394,8 +10344,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -8403,8 +10355,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -8412,8 +10366,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -8421,8 +10377,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -8430,8 +10388,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -8439,8 +10399,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -8448,8 +10410,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -8457,8 +10421,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -8466,8 +10432,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -8475,8 +10443,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -8484,8 +10454,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -8493,8 +10465,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -8502,8 +10476,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -8511,8 +10487,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -8520,8 +10498,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -8529,8 +10509,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -8538,8 +10520,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -8547,8 +10531,10 @@
},
{
"BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb",
+ "Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration",
"UMask": "0x2",
@@ -8556,8 +10542,10 @@
},
{
"BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle",
+ "Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle",
"UMask": "0x1",
@@ -8565,8 +10553,10 @@
},
{
"BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1",
+ "Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit",
"UMask": "0x4",
@@ -8574,8 +10564,10 @@
},
{
"BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2",
+ "Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit",
"UMask": "0x8",
@@ -8583,8 +10575,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only)",
"UMask": "0x1",
@@ -8592,8 +10586,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events : Any in BGF Path",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)",
"UMask": "0x2",
@@ -8601,8 +10597,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 1",
"UMask": "0x10",
@@ -8610,8 +10608,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 2",
"UMask": "0x20",
@@ -8619,8 +10619,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events : No D2K For Arb",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit",
"UMask": "0x4",
@@ -8628,8 +10630,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits",
"UMask": "0x8",
@@ -8637,8 +10641,10 @@
},
{
"BriefDescription": "Credit Occupancy : Credits Consumed",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle",
"UMask": "0x80",
@@ -8646,8 +10652,10 @@
},
{
"BriefDescription": "Credit Occupancy : D2K Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles",
"UMask": "0x10",
@@ -8655,8 +10663,10 @@
},
{
"BriefDescription": "Credit Occupancy : Packets in BGF FIFO",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo",
"UMask": "0x2",
@@ -8664,8 +10674,10 @@
},
{
"BriefDescription": "Credit Occupancy : Packets in BGF Path",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)",
"UMask": "0x4",
@@ -8673,8 +10685,10 @@
},
{
"BriefDescription": "Credit Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only",
"UMask": "0x40",
@@ -8682,8 +10696,10 @@
},
{
"BriefDescription": "Credit Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo",
"UMask": "0x20",
@@ -8691,8 +10707,10 @@
},
{
"BriefDescription": "Credit Occupancy : Transmit Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles",
"UMask": "0x8",
@@ -8700,8 +10718,10 @@
},
{
"BriefDescription": "Credit Occupancy : VNA In Use",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles",
"UMask": "0x1",
@@ -8709,8 +10729,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -8718,8 +10740,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -8727,8 +10751,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -8736,8 +10762,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -8745,8 +10773,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -8754,8 +10784,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -8763,8 +10795,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -8772,8 +10806,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -8781,8 +10817,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -8790,8 +10828,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -8799,8 +10839,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -8808,8 +10850,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -8817,8 +10861,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -8826,8 +10872,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -8835,8 +10883,10 @@
},
{
"BriefDescription": "Data Flit Not Sent : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection",
"UMask": "0x1",
@@ -8844,8 +10894,10 @@
},
{
"BriefDescription": "Data Flit Not Sent : No BGF Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent",
"UMask": "0x8",
@@ -8853,8 +10905,10 @@
},
{
"BriefDescription": "Data Flit Not Sent : No TxQ Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent",
"UMask": "0x10",
@@ -8862,8 +10916,10 @@
},
{
"BriefDescription": "Data Flit Not Sent : TSV High",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high",
"UMask": "0x2",
@@ -8871,8 +10927,10 @@
},
{
"BriefDescription": "Data Flit Not Sent : Cycle valid for Flit",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission",
"UMask": "0x4",
@@ -8880,8 +10938,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0",
"UMask": "0x1",
@@ -8889,8 +10949,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit)",
"UMask": "0x10",
@@ -8898,8 +10960,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message",
"UMask": "0x8",
@@ -8907,8 +10971,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending completion fifo is full",
"UMask": "0x40",
@@ -8916,8 +10982,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage",
"UMask": "0x20",
@@ -8925,8 +10993,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic",
"UMask": "0x4",
@@ -8934,8 +11004,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1",
"UMask": "0x2",
@@ -8943,8 +11015,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request naturally serviced during hold-off period",
"UMask": "0x4",
@@ -8952,8 +11026,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request forcibly serviced during service window",
"UMask": "0x8",
@@ -8961,8 +11037,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request received from link layer while idle (with no slot 2 request active immediately prior)",
"UMask": "0x1",
@@ -8970,8 +11048,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request withdrawn during hold-off period or service window",
"UMask": "0x2",
@@ -8979,16 +11059,20 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence",
"UMask": "0x2",
@@ -8996,8 +11080,10 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0",
"UMask": "0x4",
@@ -9005,8 +11091,10 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit",
"UMask": "0x10",
@@ -9014,8 +11102,10 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed",
"UMask": "0x20",
@@ -9023,8 +11113,10 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available",
"UMask": "0x40",
@@ -9032,8 +11124,10 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1",
"UMask": "0x8",
@@ -9041,8 +11135,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1 : Accumulate",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles",
"UMask": "0x1",
@@ -9050,8 +11146,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1 : Accumulate Ready",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit",
"UMask": "0x2",
@@ -9059,8 +11157,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted",
"UMask": "0x4",
@@ -9068,8 +11168,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked",
"UMask": "0x8",
@@ -9077,8 +11179,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted",
"UMask": "0x80",
@@ -9086,8 +11190,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead",
"UMask": "0x10",
@@ -9095,8 +11201,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success",
"UMask": "0x20",
@@ -9104,8 +11212,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success",
"UMask": "0x40",
@@ -9113,8 +11223,10 @@
},
{
"BriefDescription": "Flit Gen - Header 2 : Parallel Ok",
+ "Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence",
"UMask": "0x4",
@@ -9122,8 +11234,10 @@
},
{
"BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished",
+ "Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence",
"UMask": "0x10",
@@ -9131,8 +11245,10 @@
},
{
"BriefDescription": "Flit Gen - Header 2 : Parallel Message",
+ "Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence",
"UMask": "0x8",
@@ -9140,8 +11256,10 @@
},
{
"BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall",
+ "Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected",
"UMask": "0x1",
@@ -9149,8 +11267,10 @@
},
{
"BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message",
+ "Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle",
"UMask": "0x2",
@@ -9158,8 +11278,10 @@
},
{
"BriefDescription": "Sent Header Flit : One Message",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit",
"UMask": "0x1",
@@ -9167,8 +11289,10 @@
},
{
"BriefDescription": "Sent Header Flit : One Message in non-VNA",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit",
"UMask": "0x8",
@@ -9176,8 +11300,10 @@
},
{
"BriefDescription": "Sent Header Flit : Two Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : Two Messages : Two messages in flit; VNA flit",
"UMask": "0x2",
@@ -9185,8 +11311,10 @@
},
{
"BriefDescription": "Sent Header Flit : Three Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : Three Messages : Three messages in flit; VNA flit",
"UMask": "0x4",
@@ -9194,32 +11322,40 @@
},
{
"BriefDescription": "Sent Header Flit : One Slot Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : Two Slots Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : All Slots Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Header Not Sent : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection",
"UMask": "0x1",
@@ -9227,8 +11363,10 @@
},
{
"BriefDescription": "Header Not Sent : No BGF Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available",
"UMask": "0x8",
@@ -9236,8 +11374,10 @@
},
{
"BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit",
"UMask": "0x20",
@@ -9245,8 +11385,10 @@
},
{
"BriefDescription": "Header Not Sent : No TxQ Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available",
"UMask": "0x10",
@@ -9254,8 +11396,10 @@
},
{
"BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit",
"UMask": "0x40",
@@ -9263,8 +11407,10 @@
},
{
"BriefDescription": "Header Not Sent : TSV High",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high",
"UMask": "0x2",
@@ -9272,8 +11418,10 @@
},
{
"BriefDescription": "Header Not Sent : Cycle valid for Flit",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission",
"UMask": "0x4",
@@ -9281,8 +11429,10 @@
},
{
"BriefDescription": "Message Held : Can't Slot AD",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})",
"UMask": "0x10",
@@ -9290,8 +11440,10 @@
},
{
"BriefDescription": "Message Held : Can't Slot BL",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})",
"UMask": "0x20",
@@ -9299,8 +11451,10 @@
},
{
"BriefDescription": "Message Held : Parallel Attempt",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel",
"UMask": "0x4",
@@ -9308,8 +11462,10 @@
},
{
"BriefDescription": "Message Held : Parallel Success",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in parallel",
"UMask": "0x8",
@@ -9317,8 +11473,10 @@
},
{
"BriefDescription": "Message Held : VN0",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit",
"UMask": "0x1",
@@ -9326,8 +11484,10 @@
},
{
"BriefDescription": "Message Held : VN1",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.VN1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit",
"UMask": "0x2",
@@ -9335,8 +11495,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -9344,8 +11506,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -9353,8 +11517,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -9362,8 +11528,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -9371,8 +11539,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -9380,8 +11550,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -9389,8 +11561,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -9398,8 +11572,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -9407,8 +11583,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -9416,8 +11594,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -9425,8 +11605,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -9434,8 +11616,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -9443,8 +11627,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -9452,8 +11638,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -9461,8 +11649,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -9470,8 +11660,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -9479,8 +11671,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -9488,8 +11682,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -9497,8 +11693,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -9506,8 +11704,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -9515,8 +11715,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -9524,8 +11726,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -9533,8 +11737,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -9542,8 +11748,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -9551,8 +11759,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -9560,8 +11770,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -9569,8 +11781,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -9578,8 +11792,10 @@
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -9587,8 +11803,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : REQ on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -9596,8 +11814,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : RSP on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -9605,8 +11825,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : SNP on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -9614,8 +11836,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : NCB on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -9623,8 +11847,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : NCS on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -9632,8 +11858,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : RSP on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -9641,8 +11869,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : WB on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -9650,8 +11880,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : REQ on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -9659,8 +11891,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : RSP on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -9668,8 +11902,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : SNP on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -9677,8 +11913,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : NCB on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -9686,8 +11924,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : NCS on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -9695,8 +11935,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : RSP on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -9704,8 +11946,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : WB on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -9713,8 +11957,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Any In Use",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Any In Use : At least one remote vna credit is in use",
"UMask": "0x20",
@@ -9722,8 +11968,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Corrected",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle",
"UMask": "0x1",
@@ -9731,8 +11979,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Level < 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available)",
"UMask": "0x2",
@@ -9740,8 +11990,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Level < 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible",
"UMask": "0x10",
@@ -9749,8 +12001,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Level < 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna",
"UMask": "0x4",
@@ -9758,8 +12012,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Level < 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible",
"UMask": "0x8",
@@ -9767,8 +12023,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credit count was less than 5 and allocation to ad or bl messages was required",
"UMask": "0x2",
@@ -9776,8 +12034,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credit count was less than 10 and allocation to vn0 or vn1 was required",
"UMask": "0x1",
@@ -9785,8 +12045,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn0, remote vna credits were allocated only to ad messages, not to bl",
"UMask": "0x10",
@@ -9794,8 +12056,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn0, remote vna credits were allocated only to bl messages, not to ad",
"UMask": "0x20",
@@ -9803,8 +12067,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credits were allocated only to vn0, not to vn1",
"UMask": "0x4",
@@ -9812,8 +12078,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn1, remote vna credits were allocated only to ad messages, not to bl",
"UMask": "0x40",
@@ -9821,8 +12089,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn1, remote vna credits were allocated only to bl messages, not to ad",
"UMask": "0x80",
@@ -9830,8 +12100,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credits were allocated only to vn1, not to vn0",
"UMask": "0x8",
@@ -9839,8 +12111,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x11",
@@ -9848,8 +12122,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
@@ -9857,8 +12133,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x1",
@@ -9866,8 +12144,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x44",
@@ -9875,8 +12155,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
@@ -9884,8 +12166,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x4",
@@ -9893,8 +12177,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
@@ -9902,8 +12188,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x10",
@@ -9911,8 +12199,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x1",
@@ -9920,8 +12210,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
"UMask": "0x2",
@@ -9929,8 +12221,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x80",
@@ -9938,8 +12232,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x44",
@@ -9947,8 +12243,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x40",
@@ -9956,8 +12254,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x4",
@@ -9965,8 +12265,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
"UMask": "0x8",
@@ -9974,8 +12276,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -9983,8 +12287,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x10",
@@ -9992,8 +12298,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x1",
@@ -10001,8 +12309,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x2",
@@ -10010,8 +12320,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -10019,8 +12331,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x40",
@@ -10028,8 +12342,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x4",
@@ -10037,8 +12353,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x80",
@@ -10046,8 +12364,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x8",
@@ -10055,16 +12375,20 @@
},
{
"BriefDescription": "Transgress Injection Starvation",
+ "Counter": "0,1,2,3",
"EventCode": "0xe4",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
@@ -10072,8 +12396,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
@@ -10081,8 +12407,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
@@ -10090,8 +12418,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
@@ -10099,8 +12429,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
@@ -10108,8 +12440,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
@@ -10117,8 +12451,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x40",
@@ -10126,8 +12462,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
@@ -10135,8 +12473,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
@@ -10144,8 +12484,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
@@ -10153,8 +12495,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
@@ -10162,8 +12506,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
@@ -10171,8 +12517,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
@@ -10180,8 +12528,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
@@ -10189,8 +12539,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
@@ -10198,8 +12550,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
@@ -10207,8 +12561,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
@@ -10216,8 +12572,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
@@ -10225,8 +12583,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -10234,8 +12594,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -10243,8 +12605,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -10252,8 +12616,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -10261,8 +12627,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -10270,8 +12638,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -10279,8 +12649,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -10288,8 +12660,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -10297,8 +12671,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -10306,8 +12682,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -10315,8 +12693,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -10324,8 +12704,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -10333,8 +12715,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -10342,8 +12726,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -10351,8 +12737,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -10360,8 +12748,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -10369,8 +12759,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -10378,8 +12770,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -10387,8 +12781,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -10396,8 +12792,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -10405,8 +12803,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -10414,8 +12814,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -10423,8 +12825,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -10432,8 +12836,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -10441,8 +12847,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -10450,8 +12858,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -10459,8 +12869,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -10468,8 +12880,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -10477,8 +12891,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -10486,8 +12902,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -10495,8 +12913,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -10504,8 +12924,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -10513,8 +12935,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -10522,8 +12946,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -10531,8 +12957,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -10540,8 +12968,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -10549,8 +12979,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -10558,8 +12990,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -10567,8 +13001,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -10576,8 +13012,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -10585,8 +13023,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -10594,8 +13034,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -10603,8 +13045,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -10612,8 +13056,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -10621,8 +13067,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN0 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x1",
@@ -10630,8 +13078,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x4",
@@ -10639,8 +13089,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN0 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x2",
@@ -10648,8 +13100,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN0 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x8",
@@ -10657,8 +13111,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN1 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x10",
@@ -10666,8 +13122,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x40",
@@ -10675,8 +13133,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN1 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x20",
@@ -10684,8 +13144,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN1 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x80",
@@ -10693,8 +13155,10 @@
},
{
"BriefDescription": "AD FlowQ Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x1",
@@ -10702,8 +13166,10 @@
},
{
"BriefDescription": "AD FlowQ Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x2",
@@ -10711,8 +13177,10 @@
},
{
"BriefDescription": "AD FlowQ Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x4",
@@ -10720,8 +13188,10 @@
},
{
"BriefDescription": "AD FlowQ Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x8",
@@ -10729,8 +13199,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x1",
@@ -10738,8 +13210,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x4",
@@ -10747,8 +13221,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x2",
@@ -10756,8 +13232,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x8",
@@ -10765,8 +13243,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x10",
@@ -10774,8 +13254,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x40",
@@ -10783,8 +13265,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x20",
@@ -10792,8 +13276,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x80",
@@ -10801,8 +13287,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x1",
@@ -10810,8 +13298,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x4",
@@ -10819,8 +13309,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x2",
@@ -10828,8 +13320,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x8",
@@ -10837,8 +13331,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x10",
@@ -10846,8 +13342,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x40",
@@ -10855,8 +13353,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x20",
@@ -10864,78 +13364,98 @@
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages",
+ "Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages",
+ "Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages",
+ "Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages",
+ "Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages",
+ "Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "AK Flow Q Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "AK Flow Q Occupancy",
+ "Counter": "0",
"EventCode": "0x1E",
"EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for BL : VN0 NCB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x4",
@@ -10943,8 +13463,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN0 NCS Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x8",
@@ -10952,8 +13474,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x1",
@@ -10961,8 +13485,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN0 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x2",
@@ -10970,8 +13496,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN1 NCS Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x40",
@@ -10979,8 +13507,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN1 NCB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x80",
@@ -10988,8 +13518,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x10",
@@ -10997,8 +13529,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN1 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x20",
@@ -11006,8 +13540,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x1",
@@ -11015,8 +13551,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x4",
@@ -11024,8 +13562,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x2",
@@ -11033,8 +13573,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x8",
@@ -11042,8 +13584,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x10",
@@ -11051,8 +13595,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x40",
@@ -11060,8 +13606,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x20",
@@ -11069,8 +13617,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x80",
@@ -11078,8 +13628,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x1",
@@ -11087,8 +13639,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x2",
@@ -11096,8 +13650,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x8",
@@ -11105,8 +13661,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x4",
@@ -11114,8 +13672,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x10",
@@ -11123,8 +13683,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN1 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x20",
@@ -11132,8 +13694,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x80",
@@ -11141,8 +13705,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x40",
@@ -11150,120 +13716,150 @@
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
+ "Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages",
+ "Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
+ "Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
+ "Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages",
+ "Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
+ "Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
+ "Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
+ "Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
+ "Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
+ "Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -11271,8 +13867,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -11280,8 +13878,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -11289,8 +13889,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -11298,8 +13900,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -11307,8 +13911,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -11316,8 +13922,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -11325,8 +13933,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -11334,8 +13944,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -11343,8 +13955,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -11352,8 +13966,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x80",
@@ -11361,8 +13977,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -11370,8 +13988,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -11379,8 +13999,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -11388,8 +14010,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
@@ -11397,8 +14021,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -11406,8 +14032,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -11415,8 +14043,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -11424,8 +14054,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -11433,8 +14065,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -11442,8 +14076,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -11451,8 +14087,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -11460,8 +14098,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -11469,8 +14109,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -11478,8 +14120,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -11487,8 +14131,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -11496,8 +14142,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -11505,8 +14153,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -11514,8 +14164,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -11523,8 +14175,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -11532,8 +14186,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -11541,8 +14197,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -11550,8 +14208,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -11559,8 +14219,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -11568,8 +14230,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -11577,8 +14241,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -11586,8 +14252,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -11595,8 +14263,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -11604,8 +14274,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -11613,8 +14285,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -11622,8 +14296,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -11631,8 +14307,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -11640,8 +14318,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x11",
@@ -11649,8 +14329,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x10",
@@ -11658,8 +14340,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x1",
@@ -11667,8 +14351,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x2",
@@ -11676,8 +14362,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x80",
@@ -11685,8 +14373,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x44",
@@ -11694,8 +14384,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x40",
@@ -11703,8 +14395,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x4",
@@ -11712,8 +14406,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x8",
@@ -11721,8 +14417,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -11730,8 +14428,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -11739,8 +14439,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -11748,8 +14450,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -11757,8 +14461,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -11766,8 +14472,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -11775,8 +14483,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -11784,8 +14494,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -11793,8 +14505,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -11802,8 +14516,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x1",
@@ -11811,8 +14527,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x1",
@@ -11820,8 +14538,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x2",
@@ -11829,8 +14549,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x80",
@@ -11838,8 +14560,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x4",
@@ -11847,8 +14571,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x4",
@@ -11856,8 +14582,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x8",
@@ -11865,8 +14593,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -11874,8 +14604,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -11883,8 +14615,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -11892,8 +14626,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -11901,8 +14637,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -11910,8 +14648,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -11919,8 +14659,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -11928,8 +14670,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x20",
@@ -11937,8 +14681,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -11946,8 +14692,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -11955,8 +14703,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
@@ -11964,8 +14714,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -11973,8 +14725,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -11982,8 +14736,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -11991,8 +14747,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -12000,8 +14758,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -12009,8 +14769,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -12018,8 +14780,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -12027,8 +14791,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -12036,8 +14802,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -12045,8 +14813,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -12054,8 +14824,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -12063,8 +14835,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -12072,8 +14846,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -12081,8 +14857,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -12090,8 +14868,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -12099,8 +14879,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -12108,8 +14890,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -12117,8 +14901,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -12126,8 +14912,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -12135,8 +14923,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -12144,8 +14934,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -12153,8 +14945,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -12162,8 +14956,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -12171,8 +14967,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -12180,8 +14978,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -12189,8 +14989,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -12198,8 +15000,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -12207,8 +15011,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -12216,8 +15022,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -12225,8 +15033,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
@@ -12234,8 +15044,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x10",
@@ -12243,8 +15055,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
@@ -12252,8 +15066,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
@@ -12261,8 +15077,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x4",
@@ -12270,8 +15088,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x40",
@@ -12279,8 +15099,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x8",
@@ -12288,8 +15110,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
@@ -12297,8 +15121,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
@@ -12306,8 +15132,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -12315,8 +15143,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -12324,8 +15154,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -12333,8 +15165,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -12342,8 +15176,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -12351,8 +15187,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -12360,8 +15198,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -12369,8 +15209,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -12378,8 +15220,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -12387,8 +15231,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
@@ -12396,8 +15242,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x10",
@@ -12405,8 +15253,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
@@ -12414,8 +15264,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x20",
@@ -12423,8 +15275,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
@@ -12432,8 +15286,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x40",
@@ -12441,8 +15297,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x8",
@@ -12450,8 +15308,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
@@ -12459,8 +15319,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
@@ -12468,8 +15330,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
@@ -12477,8 +15341,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x2",
@@ -12486,8 +15352,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x8",
@@ -12495,8 +15363,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x4",
@@ -12504,8 +15374,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x10",
@@ -12513,8 +15385,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x40",
@@ -12522,8 +15396,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x20",
@@ -12531,8 +15407,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VNA",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring",
"UMask": "0x1",
@@ -12540,8 +15418,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x4",
@@ -12549,8 +15429,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x2",
@@ -12558,8 +15440,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x8",
@@ -12567,8 +15451,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x20",
@@ -12576,8 +15462,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x10",
@@ -12585,8 +15473,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x40",
@@ -12594,8 +15484,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VNA",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x1",
@@ -12603,16 +15495,20 @@
},
{
"BriefDescription": "FlowQ Generated Prefetch",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -12620,8 +15516,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -12629,8 +15527,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -12638,8 +15538,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -12647,8 +15549,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -12656,8 +15560,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -12665,8 +15571,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -12674,8 +15582,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -12683,8 +15593,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -12692,8 +15604,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -12701,8 +15615,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -12710,8 +15626,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -12719,8 +15637,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -12728,8 +15648,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -12737,8 +15659,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -12746,8 +15670,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -12755,8 +15681,10 @@
},
{
"BriefDescription": "Vertical IV Ring in Use : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
@@ -12764,8 +15692,10 @@
},
{
"BriefDescription": "Vertical IV Ring in Use : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
@@ -12773,8 +15703,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -12782,8 +15714,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -12791,8 +15725,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -12800,8 +15736,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -12809,8 +15747,10 @@
},
{
"BriefDescription": "VN0 Credit Used : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -12818,8 +15758,10 @@
},
{
"BriefDescription": "VN0 Credit Used : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -12827,8 +15769,10 @@
},
{
"BriefDescription": "VN0 Credit Used : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -12836,8 +15780,10 @@
},
{
"BriefDescription": "VN0 Credit Used : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -12845,8 +15791,10 @@
},
{
"BriefDescription": "VN0 Credit Used : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -12854,8 +15802,10 @@
},
{
"BriefDescription": "VN0 Credit Used : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -12863,8 +15813,10 @@
},
{
"BriefDescription": "VN0 No Credits : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -12872,8 +15824,10 @@
},
{
"BriefDescription": "VN0 No Credits : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -12881,8 +15835,10 @@
},
{
"BriefDescription": "VN0 No Credits : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -12890,8 +15846,10 @@
},
{
"BriefDescription": "VN0 No Credits : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -12899,8 +15857,10 @@
},
{
"BriefDescription": "VN0 No Credits : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -12908,8 +15868,10 @@
},
{
"BriefDescription": "VN0 No Credits : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -12917,8 +15879,10 @@
},
{
"BriefDescription": "VN1 Credit Used : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -12926,8 +15890,10 @@
},
{
"BriefDescription": "VN1 Credit Used : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -12935,8 +15901,10 @@
},
{
"BriefDescription": "VN1 Credit Used : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -12944,8 +15912,10 @@
},
{
"BriefDescription": "VN1 Credit Used : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -12953,8 +15923,10 @@
},
{
"BriefDescription": "VN1 Credit Used : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -12962,8 +15934,10 @@
},
{
"BriefDescription": "VN1 Credit Used : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -12971,8 +15945,10 @@
},
{
"BriefDescription": "VN1 No Credits : WB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -12980,8 +15956,10 @@
},
{
"BriefDescription": "VN1 No Credits : NCB on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -12989,8 +15967,10 @@
},
{
"BriefDescription": "VN1 No Credits : REQ on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -12998,8 +15978,10 @@
},
{
"BriefDescription": "VN1 No Credits : RSP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -13007,8 +15989,10 @@
},
{
"BriefDescription": "VN1 No Credits : SNP on AD",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -13016,8 +16000,10 @@
},
{
"BriefDescription": "VN1 No Credits : RSP on BL",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -13025,168 +16011,210 @@
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x82",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa0",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x81",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x90",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x84",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc0",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.ARB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message is making arbitration request",
"UMask": "0x4",
@@ -13194,8 +16222,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message arrived in ingress pipeline",
"UMask": "0x1",
@@ -13203,8 +16233,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message took bypass path",
"UMask": "0x2",
@@ -13212,8 +16244,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message was slotted into flit (non bypass)",
"UMask": "0x10",
@@ -13221,8 +16255,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message lost arbitration",
"UMask": "0x8",
@@ -13230,8 +16266,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message was dropped because it became too old",
"UMask": "0x20",
@@ -13239,8 +16277,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full",
"UMask": "0x20",
@@ -13248,6 +16288,7 @@
},
{
"BriefDescription": "Number of kfclks",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_UPI_CLOCKTICKS",
"PerPkg": "1",
@@ -13256,8 +16297,10 @@
},
{
"BriefDescription": "Direct packet attempts : D2C",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
"UMask": "0x1",
@@ -13265,8 +16308,10 @@
},
{
"BriefDescription": "Direct packet attempts : D2K",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
"UMask": "0x2",
@@ -13274,70 +16319,87 @@
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L1",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_UPI_L1_POWER_CYCLES",
"PerPkg": "1",
@@ -13346,182 +16408,228 @@
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_UPI_PHY_INIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "L1 Req Nack",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_UPI_POWER_L1_NACK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
"Unit": "UPI"
},
{
"BriefDescription": "L1 Req (same as L1 Ack).",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_UPI_POWER_L1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0p",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_UPI_RxL0_POWER_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xe",
@@ -13529,8 +16637,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10e",
@@ -13538,8 +16648,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xf",
@@ -13547,8 +16659,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10f",
@@ -13556,8 +16670,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x8",
@@ -13565,8 +16681,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x108",
@@ -13574,8 +16692,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x1aa",
@@ -13583,8 +16703,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x12a",
@@ -13592,8 +16714,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xc",
@@ -13601,8 +16725,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10c",
@@ -13610,8 +16736,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xa",
@@ -13619,8 +16747,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10a",
@@ -13628,8 +16758,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x9",
@@ -13637,8 +16769,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x109",
@@ -13646,8 +16780,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Writeback",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xd",
@@ -13655,8 +16791,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10d",
@@ -13664,8 +16802,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"UMask": "0x1",
@@ -13673,8 +16813,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"UMask": "0x2",
@@ -13682,8 +16824,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"UMask": "0x4",
@@ -13691,46 +16835,57 @@
},
{
"BriefDescription": "CRC Errors Detected",
+ "Counter": "0,1,2,3",
"EventCode": "0x0B",
"EventName": "UNC_UPI_RxL_CRC_ERRORS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CRC Errors Detected : Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).",
"Unit": "UPI"
},
{
"BriefDescription": "LLR Requests Sent",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.",
"Unit": "UPI"
},
{
"BriefDescription": "VN0 Credit Consumed",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "UPI"
},
{
"BriefDescription": "VN1 Credit Consumed",
+ "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "UPI"
},
{
"BriefDescription": "VNA Credit Consumed",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VNA Credit Consumed : Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : All Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
"PerPkg": "1",
@@ -13740,6 +16895,7 @@
},
{
"BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
"PerPkg": "1",
@@ -13749,8 +16905,10 @@
},
{
"BriefDescription": "Valid Flits Received : Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.DATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
"UMask": "0x8",
@@ -13758,8 +16916,10 @@
},
{
"BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.IDLE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x47",
@@ -13767,8 +16927,10 @@
},
{
"BriefDescription": "Valid Flits Received : LLCRD Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
"UMask": "0x10",
@@ -13776,8 +16938,10 @@
},
{
"BriefDescription": "Valid Flits Received : LLCTRL",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
"UMask": "0x40",
@@ -13785,6 +16949,7 @@
},
{
"BriefDescription": "Valid Flits Received : All Non Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
"PerPkg": "1",
@@ -13794,8 +16959,10 @@
},
{
"BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.NULL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
"UMask": "0x20",
@@ -13803,8 +16970,10 @@
},
{
"BriefDescription": "Valid Flits Received : Protocol Header",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
"UMask": "0x80",
@@ -13812,8 +16981,10 @@
},
{
"BriefDescription": "Valid Flits Received : Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
"UMask": "0x1",
@@ -13821,8 +16992,10 @@
},
{
"BriefDescription": "Valid Flits Received : Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
"UMask": "0x2",
@@ -13830,8 +17003,10 @@
},
{
"BriefDescription": "Valid Flits Received : Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
"UMask": "0x4",
@@ -13839,8 +17014,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"UMask": "0x1",
@@ -13848,8 +17025,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"UMask": "0x2",
@@ -13857,8 +17036,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"UMask": "0x4",
@@ -13866,8 +17047,10 @@
},
{
"BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"UMask": "0x1",
@@ -13875,8 +17058,10 @@
},
{
"BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"UMask": "0x2",
@@ -13884,8 +17069,10 @@
},
{
"BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"UMask": "0x4",
@@ -13893,118 +17080,147 @@
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0p",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
"PerPkg": "1",
@@ -14013,30 +17229,38 @@
},
{
"BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_UPI_TxL0_POWER_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xe",
@@ -14044,8 +17268,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10e",
@@ -14053,8 +17279,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xf",
@@ -14062,8 +17290,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10f",
@@ -14071,8 +17301,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x8",
@@ -14080,8 +17312,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x108",
@@ -14089,8 +17323,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x1aa",
@@ -14098,8 +17334,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x12a",
@@ -14107,8 +17345,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xc",
@@ -14116,8 +17356,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10c",
@@ -14125,8 +17367,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xa",
@@ -14134,8 +17378,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10a",
@@ -14143,8 +17389,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x9",
@@ -14152,8 +17400,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x109",
@@ -14161,8 +17411,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Writeback",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xd",
@@ -14170,8 +17422,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10d",
@@ -14179,14 +17433,17 @@
},
{
"BriefDescription": "Tx Flit Buffer Bypassed",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_UPI_TxL_BYPASSED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : All Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
"PerPkg": "1",
@@ -14196,6 +17453,7 @@
},
{
"BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
"PerPkg": "1",
@@ -14205,8 +17463,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.DATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
"UMask": "0x8",
@@ -14214,8 +17474,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Idle",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.IDLE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x47",
@@ -14223,8 +17485,10 @@
},
{
"BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
"UMask": "0x10",
@@ -14232,8 +17496,10 @@
},
{
"BriefDescription": "Valid Flits Sent : LLCTRL",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
"UMask": "0x40",
@@ -14241,6 +17507,7 @@
},
{
"BriefDescription": "Valid Flits Sent : All Non Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
"PerPkg": "1",
@@ -14250,8 +17517,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.NULL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
"UMask": "0x20",
@@ -14259,8 +17528,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Protocol Header",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
"UMask": "0x80",
@@ -14268,8 +17539,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
"UMask": "0x1",
@@ -14277,8 +17550,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
"UMask": "0x2",
@@ -14286,8 +17561,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
"UMask": "0x4",
@@ -14295,37 +17572,46 @@
},
{
"BriefDescription": "Tx Flit Buffer Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_UPI_TxL_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"Unit": "UPI"
},
{
"BriefDescription": "Tx Flit Buffer Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_UPI_TxL_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "VNA Credits Pending Return - Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
"Unit": "UPI"
},
{
"BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+ "Counter": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
@@ -14333,16 +17619,20 @@
},
{
"BriefDescription": "Message Received : Doorbell",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Message Received : Interrupt",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : Interrupt : Interrupts",
"UMask": "0x10",
@@ -14350,8 +17640,10 @@
},
{
"BriefDescription": "Message Received : IPI",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : IPI : Inter Processor Interrupts",
"UMask": "0x4",
@@ -14359,8 +17651,10 @@
},
{
"BriefDescription": "Message Received : MSI",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
"UMask": "0x2",
@@ -14368,8 +17662,10 @@
},
{
"BriefDescription": "Message Received : VLW",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.",
"UMask": "0x1",
@@ -14377,160 +17673,200 @@
},
{
"BriefDescription": "IDI Lock/SplitLock Cycles",
+ "Counter": "0,1",
"EventCode": "0x44",
"EventName": "UNC_U_LOCK_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
+ "Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
+ "Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
+ "Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
+ "Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
+ "Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
+ "Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
+ "Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
+ "Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
+ "Counter": "0,1",
"EventCode": "0x4F",
"EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
+ "Counter": "0,1",
"EventCode": "0x4F",
"EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
+ "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.",
"UMask": "0x1",
@@ -14538,32 +17874,40 @@
},
{
"BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "Counter": "0,1",
"EventCode": "0x4C",
"EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+ "Counter": "0,1",
"EventCode": "0x4C",
"EventName": "UNC_U_RACU_DRNG.RDRAND",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+ "Counter": "0,1",
"EventCode": "0x4C",
"EventName": "UNC_U_RACU_DRNG.RDSEED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "RACU Request",
+ "Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker",
"Unit": "UBOX"
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json
index 1b8a719b81a5..3c3c2cf51e1d 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json
@@ -1,70 +1,87 @@
[
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "1",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "2",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x21",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "3",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x22",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "4",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x23",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "5",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x24",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "6",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x25",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "7",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x26",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "8",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x27",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_IIO_CLOCKTICKS",
"PerPkg": "1",
@@ -73,6 +90,7 @@
},
{
"BriefDescription": "Free running counter that increments for IIO clocktick",
+ "Counter": "0",
"EventCode": "0xff",
"EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
"PerPkg": "1",
@@ -82,8 +100,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
+ "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
+ "Experimental": "1",
"FCMask": "0x04",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -92,6 +112,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
"FCMask": "0x04",
@@ -103,6 +124,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
"FCMask": "0x04",
@@ -114,6 +136,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
"FCMask": "0x04",
@@ -125,6 +148,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
"FCMask": "0x04",
@@ -136,6 +160,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
"FCMask": "0x04",
@@ -147,6 +172,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
"FCMask": "0x04",
@@ -158,6 +184,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
"FCMask": "0x04",
@@ -169,6 +196,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
"FCMask": "0x04",
@@ -180,6 +208,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
"FCMask": "0x04",
@@ -191,8 +220,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+ "Counter": "2,3",
"EventCode": "0xD5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
+ "Experimental": "1",
"FCMask": "0x04",
"PerPkg": "1",
"PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
@@ -201,6 +232,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
"FCMask": "0x04",
@@ -211,6 +243,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
"FCMask": "0x04",
@@ -221,6 +254,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
"FCMask": "0x04",
@@ -231,6 +265,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
"FCMask": "0x04",
@@ -241,6 +276,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
"FCMask": "0x04",
@@ -251,6 +287,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
"FCMask": "0x04",
@@ -261,6 +298,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
"FCMask": "0x04",
@@ -271,6 +309,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
"FCMask": "0x04",
@@ -281,6 +320,7 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
"FCMask": "0x04",
@@ -291,8 +331,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -302,8 +344,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -313,8 +357,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -324,8 +370,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -335,8 +383,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -346,8 +396,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -357,8 +409,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -368,8 +422,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -379,8 +435,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -390,8 +448,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -401,8 +461,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -412,8 +474,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -423,8 +487,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -434,8 +500,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -445,8 +513,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -456,8 +526,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -467,8 +539,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -478,8 +552,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -489,8 +565,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -500,8 +578,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -511,8 +591,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -522,8 +604,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -533,8 +617,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -544,8 +630,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -555,8 +643,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -566,8 +656,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -577,8 +669,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -588,8 +682,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -599,8 +695,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -610,8 +708,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -621,8 +721,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -632,8 +734,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -643,8 +747,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -654,8 +760,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -665,8 +773,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -676,8 +786,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -687,8 +799,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -698,8 +812,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -709,8 +825,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -720,8 +838,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -731,8 +851,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -742,8 +864,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -753,6 +877,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
"FCMask": "0x07",
@@ -764,6 +889,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
"FCMask": "0x07",
@@ -775,6 +901,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
"FCMask": "0x07",
@@ -786,6 +913,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
"FCMask": "0x07",
@@ -797,6 +925,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
"FCMask": "0x07",
@@ -808,6 +937,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
"FCMask": "0x07",
@@ -819,6 +949,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
"FCMask": "0x07",
@@ -830,6 +961,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
"FCMask": "0x07",
@@ -841,8 +973,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -852,8 +986,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -863,6 +999,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
@@ -874,6 +1011,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
@@ -885,6 +1023,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
@@ -896,6 +1035,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
@@ -907,6 +1047,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
@@ -918,6 +1059,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
@@ -929,6 +1071,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
@@ -940,6 +1083,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
@@ -951,8 +1095,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -962,8 +1108,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -973,8 +1121,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -984,8 +1134,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -995,8 +1147,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -1006,8 +1160,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -1017,8 +1173,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -1028,8 +1186,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -1039,8 +1199,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -1050,8 +1212,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -1061,8 +1225,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -1072,8 +1238,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -1083,8 +1251,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -1094,8 +1264,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -1105,8 +1277,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -1116,8 +1290,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -1127,8 +1303,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -1138,8 +1316,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -1149,8 +1329,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -1160,8 +1342,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xC0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -1171,8 +1355,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -1182,8 +1368,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -1193,8 +1381,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -1204,8 +1394,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -1215,8 +1407,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -1226,8 +1420,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -1237,8 +1433,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -1248,8 +1446,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -1259,8 +1459,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -1270,8 +1472,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -1281,8 +1485,10 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -1292,8 +1498,10 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -1303,6 +1511,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
"FCMask": "0x07",
@@ -1314,6 +1523,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
"FCMask": "0x07",
@@ -1325,6 +1535,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
"FCMask": "0x07",
@@ -1336,6 +1547,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
"FCMask": "0x07",
@@ -1347,6 +1559,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
"FCMask": "0x07",
@@ -1358,6 +1571,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
"FCMask": "0x07",
@@ -1369,6 +1583,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
"FCMask": "0x07",
@@ -1380,6 +1595,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
"FCMask": "0x07",
@@ -1391,8 +1607,10 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -1402,8 +1620,10 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -1413,6 +1633,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
"FCMask": "0x07",
@@ -1424,6 +1645,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
"FCMask": "0x07",
@@ -1435,6 +1657,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
"FCMask": "0x07",
@@ -1446,6 +1669,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
"FCMask": "0x07",
@@ -1457,6 +1681,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
"FCMask": "0x07",
@@ -1468,6 +1693,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
"FCMask": "0x07",
@@ -1479,6 +1705,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
"FCMask": "0x07",
@@ -1490,6 +1717,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
"FCMask": "0x07",
@@ -1501,8 +1729,10 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -1512,8 +1742,10 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -1523,6 +1755,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
@@ -1534,6 +1767,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
@@ -1545,6 +1779,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
@@ -1556,6 +1791,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
@@ -1567,6 +1803,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
@@ -1578,6 +1815,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
@@ -1589,6 +1827,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
@@ -1600,6 +1839,7 @@
},
{
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
@@ -1611,8 +1851,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Messages",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -1622,8 +1864,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Messages",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -1633,8 +1877,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Messages",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -1644,8 +1890,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Messages",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -1655,8 +1903,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Messages",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -1666,8 +1916,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Messages",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -1677,8 +1929,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Messages",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -1688,8 +1942,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Messages",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -1699,8 +1955,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Messages",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -1710,8 +1968,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Messages",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -1721,8 +1981,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -1732,8 +1994,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -1743,8 +2007,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -1754,8 +2020,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -1765,8 +2033,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -1776,8 +2046,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -1787,8 +2059,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -1798,8 +2072,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -1809,8 +2085,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -1820,8 +2098,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -1831,8 +2111,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -1842,8 +2124,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -1853,8 +2137,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -1864,8 +2150,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -1875,8 +2163,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -1886,8 +2176,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -1897,8 +2189,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -1908,8 +2202,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -1919,8 +2215,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -1930,8 +2228,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -1941,8 +2241,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Passing data to be written",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -1952,8 +2254,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -1963,8 +2267,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -1974,8 +2280,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -1985,8 +2293,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Request Ownership",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -1996,8 +2306,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Writing line",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2007,8 +2319,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2018,8 +2332,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2029,8 +2345,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2040,8 +2358,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2051,8 +2371,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Request Ownership",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2062,8 +2384,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Writing line",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2073,8 +2397,10 @@
},
{
"BriefDescription": ": IOTLB Hits to a 1G Page",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.1G_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.",
"UMask": "0x10",
@@ -2082,8 +2408,10 @@
},
{
"BriefDescription": ": IOTLB Hits to a 2M Page",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.2M_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.",
"UMask": "0x8",
@@ -2091,8 +2419,10 @@
},
{
"BriefDescription": ": IOTLB Hits to a 4K Page",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.4K_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.",
"UMask": "0x4",
@@ -2100,8 +2430,10 @@
},
{
"BriefDescription": ": IOTLB lookups all",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB.",
"UMask": "0x2",
@@ -2109,8 +2441,10 @@
},
{
"BriefDescription": ": Context cache hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.",
"UMask": "0x80",
@@ -2118,8 +2452,10 @@
},
{
"BriefDescription": ": Context cache lookups",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.",
"UMask": "0x40",
@@ -2127,8 +2463,10 @@
},
{
"BriefDescription": ": IOTLB lookups first",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.",
"UMask": "0x1",
@@ -2136,8 +2474,10 @@
},
{
"BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.MISSES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.",
"UMask": "0x20",
@@ -2145,8 +2485,10 @@
},
{
"BriefDescription": ": Cycles PWT full",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.",
"UMask": "0x80",
@@ -2154,8 +2496,10 @@
},
{
"BriefDescription": ": IOMMU memory access",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel",
"UMask": "0x40",
@@ -2163,8 +2507,10 @@
},
{
"BriefDescription": ": PWC Hit to a 1G page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level",
"UMask": "0x8",
@@ -2172,8 +2518,10 @@
},
{
"BriefDescription": ": PWC Hit to a 2M page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
"UMask": "0x4",
@@ -2181,8 +2529,10 @@
},
{
"BriefDescription": ": PWC Hit to a 4K page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level",
"UMask": "0x2",
@@ -2190,8 +2540,10 @@
},
{
"BriefDescription": ": PWT Hit to a 256T page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level",
"UMask": "0x10",
@@ -2199,8 +2551,10 @@
},
{
"BriefDescription": ": PageWalk cache fill",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.",
"UMask": "0x20",
@@ -2208,8 +2562,10 @@
},
{
"BriefDescription": ": PageWalk cache lookup",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.",
"UMask": "0x1",
@@ -2217,8 +2573,10 @@
},
{
"BriefDescription": ": Interrupt Entry cache hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.",
"UMask": "0x80",
@@ -2226,8 +2584,10 @@
},
{
"BriefDescription": ": Interrupt Entry cache lookup",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.",
"UMask": "0x40",
@@ -2235,8 +2595,10 @@
},
{
"BriefDescription": ": Device-selective Context cache invalidation cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events",
"UMask": "0x20",
@@ -2244,8 +2606,10 @@
},
{
"BriefDescription": ": Domain-selective Context cache invalidation cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events",
"UMask": "0x10",
@@ -2253,8 +2617,10 @@
},
{
"BriefDescription": ": Context cache global invalidation cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events",
"UMask": "0x8",
@@ -2262,8 +2628,10 @@
},
{
"BriefDescription": ": Domain-selective IOTLB invalidation cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events",
"UMask": "0x2",
@@ -2271,8 +2639,10 @@
},
{
"BriefDescription": ": Global IOTLB invalidation cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.",
"UMask": "0x1",
@@ -2280,8 +2650,10 @@
},
{
"BriefDescription": ": Page-selective IOTLB invalidation cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events",
"UMask": "0x4",
@@ -2289,8 +2661,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match",
"UMask": "0x1",
@@ -2298,8 +2672,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match",
"UMask": "0x8",
@@ -2307,8 +2683,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match",
"UMask": "0x4",
@@ -2316,8 +2694,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match",
"UMask": "0x2",
@@ -2325,8 +2705,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match",
"UMask": "0x10",
@@ -2334,8 +2716,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match",
"UMask": "0x20",
@@ -2343,8 +2727,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match",
"UMask": "0x1",
@@ -2352,8 +2738,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match",
"UMask": "0x8",
@@ -2361,8 +2749,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match",
"UMask": "0x4",
@@ -2370,8 +2760,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match",
"UMask": "0x2",
@@ -2379,8 +2771,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match",
"UMask": "0x10",
@@ -2388,8 +2782,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match",
"UMask": "0x20",
@@ -2397,15 +2793,19 @@
},
{
"BriefDescription": "Counting disabled",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_IIO_NOTHING",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IIO"
},
{
"BriefDescription": "Occupancy of outbound request queue : To device",
+ "Counter": "2,3",
"EventCode": "0xC5",
"EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2415,8 +2815,10 @@
},
{
"BriefDescription": ": Passing data to be written",
+ "Counter": "2,3",
"EventCode": "0x88",
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2426,8 +2828,10 @@
},
{
"BriefDescription": ": Issuing final read or write of line",
+ "Counter": "2,3",
"EventCode": "0x88",
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2436,8 +2840,10 @@
},
{
"BriefDescription": ": Processing response from IOMMU",
+ "Counter": "2,3",
"EventCode": "0x88",
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2446,8 +2852,10 @@
},
{
"BriefDescription": ": Issuing to IOMMU",
+ "Counter": "2,3",
"EventCode": "0x88",
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2456,8 +2864,10 @@
},
{
"BriefDescription": ": Request Ownership",
+ "Counter": "2,3",
"EventCode": "0x88",
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2467,8 +2877,10 @@
},
{
"BriefDescription": ": Writing line",
+ "Counter": "2,3",
"EventCode": "0x88",
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2478,8 +2890,10 @@
},
{
"BriefDescription": "Number requests sent to PCIe from main die : >From ITC",
+ "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2489,8 +2903,10 @@
},
{
"BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2499,8 +2915,10 @@
},
{
"BriefDescription": "Number requests PCIe makes of the main die : Drop request",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2510,6 +2928,7 @@
},
{
"BriefDescription": "Number requests PCIe makes of the main die : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
"FCMask": "0x07",
@@ -2521,8 +2940,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Abort",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2531,8 +2952,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2541,8 +2964,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2551,8 +2976,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2561,8 +2988,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2571,8 +3000,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : MsgB",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2581,8 +3012,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2591,8 +3024,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Ubox",
+ "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2601,15 +3036,19 @@
},
{
"BriefDescription": "ITC address map 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IIO"
},
{
"BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2619,8 +3058,10 @@
},
{
"BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2630,16 +3071,20 @@
},
{
"BriefDescription": "PWT occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_IIO_PWT_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.",
"Unit": "IIO"
},
{
"BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2649,8 +3094,10 @@
},
{
"BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2660,8 +3107,10 @@
},
{
"BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2671,8 +3120,10 @@
},
{
"BriefDescription": "PCIe Request - cacheline complete : Writing line",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2682,8 +3133,10 @@
},
{
"BriefDescription": "PCIe Request complete : Passing data to be written",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2693,8 +3146,10 @@
},
{
"BriefDescription": "PCIe Request complete : Issuing final read or write of line",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2704,8 +3159,10 @@
},
{
"BriefDescription": "PCIe Request complete : Processing response from IOMMU",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2715,8 +3172,10 @@
},
{
"BriefDescription": "PCIe Request complete : Issuing to IOMMU",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2726,8 +3185,10 @@
},
{
"BriefDescription": "PCIe Request complete : Request Ownership",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2737,8 +3198,10 @@
},
{
"BriefDescription": "PCIe Request complete : Writing line",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2748,8 +3211,10 @@
},
{
"BriefDescription": "PCIe Request - pass complete : Passing data to be written",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2759,8 +3224,10 @@
},
{
"BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2770,8 +3237,10 @@
},
{
"BriefDescription": "PCIe Request - pass complete : Request Ownership",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2781,8 +3250,10 @@
},
{
"BriefDescription": "PCIe Request - pass complete : Writing line",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
@@ -2792,16 +3263,20 @@
},
{
"BriefDescription": "Symbol Times on Link",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_IIO_SYMBOL_TIMES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -2811,8 +3286,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -2822,8 +3299,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -2833,8 +3312,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -2844,8 +3325,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -2855,8 +3338,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -2866,8 +3351,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -2877,8 +3364,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -2888,8 +3377,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -2899,8 +3390,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -2910,8 +3403,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -2921,8 +3416,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -2932,8 +3429,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -2943,8 +3442,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -2954,8 +3455,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -2965,8 +3468,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -2976,8 +3481,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -2987,8 +3494,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -2998,8 +3507,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -3009,8 +3520,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -3020,8 +3533,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -3031,8 +3546,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -3042,8 +3559,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -3053,8 +3572,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -3064,8 +3585,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -3075,8 +3598,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -3086,8 +3611,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -3097,8 +3624,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -3108,8 +3637,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -3119,8 +3650,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -3130,8 +3663,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -3141,8 +3676,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -3152,8 +3689,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -3163,8 +3702,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -3174,8 +3715,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -3185,8 +3728,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -3196,8 +3741,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -3207,8 +3754,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -3218,8 +3767,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -3229,8 +3780,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -3240,8 +3793,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -3251,8 +3806,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -3262,6 +3819,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
"FCMask": "0x07",
@@ -3273,6 +3831,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
"FCMask": "0x07",
@@ -3284,6 +3843,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
"FCMask": "0x07",
@@ -3295,6 +3855,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
"FCMask": "0x07",
@@ -3306,6 +3867,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
"FCMask": "0x07",
@@ -3317,6 +3879,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
"FCMask": "0x07",
@@ -3328,6 +3891,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
"FCMask": "0x07",
@@ -3339,6 +3903,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
"FCMask": "0x07",
@@ -3350,8 +3915,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -3361,8 +3928,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -3372,6 +3941,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
@@ -3383,6 +3953,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
@@ -3394,6 +3965,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
@@ -3405,6 +3977,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
@@ -3416,6 +3989,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
@@ -3427,6 +4001,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
@@ -3438,6 +4013,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
@@ -3449,6 +4025,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
@@ -3460,8 +4037,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -3471,8 +4050,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -3482,8 +4063,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -3493,8 +4076,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -3504,8 +4089,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -3515,8 +4102,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -3526,8 +4115,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -3537,8 +4128,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -3548,8 +4141,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -3559,8 +4154,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -3570,8 +4167,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -3581,8 +4180,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -3592,8 +4193,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -3603,8 +4206,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -3614,8 +4219,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -3625,8 +4232,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -3636,8 +4245,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -3647,8 +4258,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -3658,8 +4271,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -3669,8 +4284,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -3680,8 +4297,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -3691,8 +4310,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -3702,8 +4323,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -3713,8 +4336,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -3724,8 +4349,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -3735,8 +4362,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -3746,8 +4375,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -3757,8 +4388,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -3768,8 +4401,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -3779,8 +4414,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -3790,8 +4427,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -3801,6 +4440,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
"FCMask": "0x07",
@@ -3812,6 +4452,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
"FCMask": "0x07",
@@ -3823,6 +4464,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
"FCMask": "0x07",
@@ -3834,6 +4476,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
"FCMask": "0x07",
@@ -3845,6 +4488,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
"FCMask": "0x07",
@@ -3856,6 +4500,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
"FCMask": "0x07",
@@ -3867,6 +4512,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
"FCMask": "0x07",
@@ -3878,6 +4524,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
"FCMask": "0x07",
@@ -3889,8 +4536,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -3900,8 +4549,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -3911,6 +4562,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
"FCMask": "0x07",
@@ -3922,6 +4574,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
"FCMask": "0x07",
@@ -3933,6 +4586,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
"FCMask": "0x07",
@@ -3944,6 +4598,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
"FCMask": "0x07",
@@ -3955,6 +4610,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
"FCMask": "0x07",
@@ -3966,6 +4622,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
"FCMask": "0x07",
@@ -3977,6 +4634,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
"FCMask": "0x07",
@@ -3988,6 +4646,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
"FCMask": "0x07",
@@ -3999,8 +4658,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -4010,8 +4671,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -4021,6 +4684,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
@@ -4032,6 +4696,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
@@ -4043,6 +4708,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
@@ -4054,6 +4720,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
@@ -4065,6 +4732,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
@@ -4076,6 +4744,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
@@ -4087,6 +4756,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
@@ -4098,6 +4768,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
@@ -4109,8 +4780,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -4120,8 +4793,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -4131,8 +4806,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -4142,8 +4819,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -4153,8 +4832,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -4164,8 +4845,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -4175,8 +4858,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -4186,8 +4871,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -4197,8 +4884,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -4208,8 +4897,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -4219,8 +4910,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -4230,8 +4923,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -4241,8 +4936,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -4252,8 +4949,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -4263,8 +4962,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -4274,8 +4975,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -4285,8 +4988,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -4296,8 +5001,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -4307,8 +5014,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -4318,8 +5027,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -4329,8 +5040,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
@@ -4340,8 +5053,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
@@ -4351,8 +5066,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
@@ -4362,8 +5079,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
@@ -4373,8 +5092,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
@@ -4384,8 +5105,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
@@ -4395,8 +5118,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
@@ -4406,8 +5131,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
@@ -4417,8 +5144,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
@@ -4428,8 +5157,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
@@ -4439,8 +5170,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -4448,8 +5181,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -4457,8 +5192,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -4466,8 +5203,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -4475,8 +5214,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -4484,8 +5225,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -4493,8 +5236,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -4502,8 +5247,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -4511,8 +5258,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -4520,8 +5269,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -4529,8 +5280,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -4538,8 +5291,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -4547,8 +5302,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -4556,8 +5313,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -4565,8 +5324,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -4574,8 +5335,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -4583,8 +5346,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -4592,8 +5357,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -4601,8 +5368,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -4610,8 +5379,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -4619,8 +5390,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -4628,8 +5401,10 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -4637,8 +5412,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -4646,8 +5423,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -4655,8 +5434,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -4664,8 +5445,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -4673,8 +5456,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -4682,8 +5467,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -4691,8 +5478,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -4700,8 +5489,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -4709,8 +5500,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -4718,8 +5511,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -4727,8 +5522,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -4736,8 +5533,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8a",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -4745,8 +5544,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8a",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -4754,8 +5555,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8a",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -4763,8 +5566,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8a",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -4772,8 +5577,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8a",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -4781,8 +5588,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8a",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -4790,8 +5599,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x8a",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -4799,8 +5610,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x8a",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -4808,8 +5621,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8b",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -4817,8 +5632,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8b",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -4826,8 +5643,10 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8b",
"EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -4835,8 +5654,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -4844,8 +5665,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -4853,8 +5676,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -4862,8 +5687,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -4871,8 +5698,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -4880,8 +5709,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -4889,8 +5720,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -4898,8 +5731,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -4907,8 +5742,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -4916,8 +5753,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -4925,8 +5764,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -4934,8 +5775,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -4943,8 +5786,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -4952,8 +5797,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -4961,8 +5808,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -4970,8 +5819,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -4979,8 +5830,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -4988,8 +5841,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -4997,8 +5852,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -5006,8 +5863,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -5015,8 +5874,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -5024,8 +5885,10 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -5033,8 +5896,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8c",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -5042,8 +5907,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8c",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -5051,8 +5918,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8c",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -5060,8 +5929,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8c",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
@@ -5069,8 +5940,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8c",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
@@ -5078,8 +5951,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8c",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
@@ -5087,8 +5962,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8c",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
@@ -5096,8 +5973,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8c",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
@@ -5105,8 +5984,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8d",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
@@ -5114,8 +5995,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8d",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
@@ -5123,8 +6006,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8d",
"EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
@@ -5132,8 +6017,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -5141,8 +6028,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -5150,8 +6039,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -5159,8 +6050,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
@@ -5168,8 +6061,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
@@ -5177,8 +6072,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
@@ -5186,8 +6083,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
@@ -5195,8 +6094,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
@@ -5204,8 +6105,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0x8f",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
@@ -5213,8 +6116,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0x8f",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
@@ -5222,8 +6127,10 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0x8f",
"EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
@@ -5231,6 +6138,7 @@
},
{
"BriefDescription": "Clockticks of the mesh to PCI (M2P)",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M2P_CLOCKTICKS",
"PerPkg": "1",
@@ -5239,6 +6147,7 @@
},
{
"BriefDescription": "CMS Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M2P_CMS_CLOCKTICKS",
"PerPkg": "1",
@@ -5246,8 +6155,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Local",
+ "Counter": "0,1,2,3",
"EventCode": "0xaf",
"EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
"UMask": "0x4",
@@ -5255,8 +6166,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0xaf",
"EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
"UMask": "0x8",
@@ -5264,8 +6177,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xaf",
"EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
"UMask": "0x40",
@@ -5273,8 +6188,10 @@
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "Counter": "0,1,2,3",
"EventCode": "0xaf",
"EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
@@ -5282,8 +6199,10 @@
},
{
"BriefDescription": "Distress signal asserted : Horizontal",
+ "Counter": "0,1,2,3",
"EventCode": "0xaf",
"EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x2",
@@ -5291,8 +6210,10 @@
},
{
"BriefDescription": "Distress signal asserted : PMM Local",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x10",
@@ -5300,8 +6221,10 @@
},
{
"BriefDescription": "Distress signal asserted : PMM Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x20",
@@ -5309,8 +6232,10 @@
},
{
"BriefDescription": "Distress signal asserted : Vertical",
+ "Counter": "0,1,2,3",
"EventCode": "0xaf",
"EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x1",
@@ -5318,8 +6243,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x4",
@@ -5327,8 +6254,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x1",
@@ -5336,8 +6265,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb6",
"EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -5345,8 +6276,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb6",
"EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -5354,8 +6287,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb6",
"EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -5363,8 +6298,10 @@
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb6",
"EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -5372,8 +6309,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xbb",
"EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -5381,8 +6320,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xbb",
"EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -5390,8 +6331,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xbb",
"EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -5399,8 +6342,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xbb",
"EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -5408,8 +6353,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb7",
"EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -5417,8 +6364,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb7",
"EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -5426,8 +6375,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb7",
"EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -5435,8 +6386,10 @@
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb7",
"EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -5444,8 +6397,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -5453,8 +6408,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -5462,8 +6419,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -5471,8 +6430,10 @@
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -5480,8 +6441,10 @@
},
{
"BriefDescription": "Horizontal IV Ring in Use : Left",
+ "Counter": "0,1,2,3",
"EventCode": "0xb9",
"EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
@@ -5489,8 +6452,10 @@
},
{
"BriefDescription": "Horizontal IV Ring in Use : Right",
+ "Counter": "0,1,2,3",
"EventCode": "0xb9",
"EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
@@ -5498,8 +6463,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
"UMask": "0x1",
@@ -5507,8 +6474,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
"UMask": "0x2",
@@ -5516,8 +6485,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
"UMask": "0x4",
@@ -5525,8 +6496,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
"UMask": "0x8",
@@ -5534,8 +6507,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
"UMask": "0x10",
@@ -5543,8 +6518,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
"UMask": "0x20",
@@ -5552,8 +6529,10 @@
},
{
"BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.",
"UMask": "0x8",
@@ -5561,8 +6540,10 @@
},
{
"BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.",
"UMask": "0x10",
@@ -5570,8 +6551,10 @@
},
{
"BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.",
"UMask": "0x20",
@@ -5579,8 +6562,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
"UMask": "0x1",
@@ -5588,8 +6573,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
"UMask": "0x2",
@@ -5597,8 +6584,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
"UMask": "0x4",
@@ -5606,8 +6595,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
"UMask": "0x8",
@@ -5615,8 +6606,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
"UMask": "0x10",
@@ -5624,8 +6617,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
"UMask": "0x20",
@@ -5633,912 +6628,1140 @@
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Shared Credits Returned : Agent0",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Shared Credits Returned : Agent1",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Shared Credits Returned : Agent2",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4b",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4b",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4b",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4b",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "P2P Credit Occupancy : All",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "P2P Credit Occupancy : Local NCB",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "P2P Credit Occupancy : Local NCS",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "P2P Credit Occupancy : Remote NCB",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "P2P Credit Occupancy : Remote NCS",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Dedicated Credits Received : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Dedicated Credits Received : Local NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Dedicated Credits Received : Local NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Dedicated Credits Received : Remote NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Dedicated Credits Received : Remote NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Shared Credits Received : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Shared Credits Received : Local NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Shared Credits Received : Local NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Shared Credits Received : Remote NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Shared Credits Received : Remote NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4d",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4d",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4d",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xac",
"EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x1",
@@ -6546,8 +7769,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xac",
"EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x2",
@@ -6555,8 +7780,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "Counter": "0,1,2,3",
"EventCode": "0xac",
"EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x4",
@@ -6564,8 +7791,10 @@
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xac",
"EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x8",
@@ -6573,8 +7802,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xaa",
"EventName": "UNC_M2P_RING_BOUNCES_VERT.AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x1",
@@ -6582,8 +7813,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xaa",
"EventName": "UNC_M2P_RING_BOUNCES_VERT.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x2",
@@ -6591,8 +7824,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "Counter": "0,1,2,3",
"EventCode": "0xaa",
"EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x10",
@@ -6600,8 +7835,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xaa",
"EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x4",
@@ -6609,8 +7846,10 @@
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xaa",
"EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x8",
@@ -6618,95 +7857,119 @@
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xad",
"EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xad",
"EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xad",
"EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "Counter": "0,1,2,3",
"EventCode": "0xad",
"EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xad",
"EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "Counter": "0,1,2,3",
"EventCode": "0xab",
"EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xab",
"EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring",
+ "Counter": "0,1,2,3",
"EventCode": "0xab",
"EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "Counter": "0,1,2,3",
"EventCode": "0xab",
"EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xab",
"EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Source Throttle",
+ "Counter": "0,1,2,3",
"EventCode": "0xae",
"EventName": "UNC_M2P_RING_SRC_THRTL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x80",
@@ -6714,8 +7977,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x1",
@@ -6723,8 +7988,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x2",
@@ -6732,8 +7999,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x4",
@@ -6741,8 +8010,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x20",
@@ -6750,8 +8021,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x40",
@@ -6759,8 +8032,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x8",
@@ -6768,8 +8043,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x10",
@@ -6777,8 +8054,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x80",
@@ -6786,8 +8065,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x1",
@@ -6795,8 +8076,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x2",
@@ -6804,8 +8087,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x4",
@@ -6813,8 +8098,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x20",
@@ -6822,8 +8109,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x40",
@@ -6831,8 +8120,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x8",
@@ -6840,8 +8131,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x10",
@@ -6849,8 +8142,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xe5",
"EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x11",
@@ -6858,8 +8153,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe5",
"EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
@@ -6867,8 +8164,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe5",
"EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x1",
@@ -6876,8 +8175,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xe5",
"EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x44",
@@ -6885,8 +8186,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe5",
"EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
@@ -6894,8 +8197,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe5",
"EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x4",
@@ -6903,8 +8208,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
@@ -6912,8 +8219,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x10",
@@ -6921,8 +8230,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x1",
@@ -6930,8 +8241,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
"UMask": "0x2",
@@ -6939,8 +8252,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x80",
@@ -6948,8 +8263,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x44",
@@ -6957,8 +8274,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x40",
@@ -6966,8 +8285,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x4",
@@ -6975,8 +8296,10 @@
},
{
"BriefDescription": "Transgress Ingress Bypass : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
"UMask": "0x8",
@@ -6984,8 +8307,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -6993,8 +8318,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x10",
@@ -7002,8 +8329,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x1",
@@ -7011,8 +8340,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x2",
@@ -7020,8 +8351,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -7029,8 +8362,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x40",
@@ -7038,8 +8373,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x4",
@@ -7047,8 +8384,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.IFV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x80",
@@ -7056,8 +8395,10 @@
},
{
"BriefDescription": "Transgress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x8",
@@ -7065,16 +8406,20 @@
},
{
"BriefDescription": "Transgress Injection Starvation",
+ "Counter": "0,1,2,3",
"EventCode": "0xe4",
"EventName": "UNC_M2P_RxR_CRD_STARVED_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
@@ -7082,8 +8427,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
@@ -7091,8 +8438,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
@@ -7100,8 +8449,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
@@ -7109,8 +8460,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
@@ -7118,8 +8471,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
@@ -7127,8 +8482,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x40",
@@ -7136,8 +8493,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
@@ -7145,8 +8504,10 @@
},
{
"BriefDescription": "Transgress Ingress Allocations : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
@@ -7154,8 +8515,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
@@ -7163,8 +8526,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
@@ -7172,8 +8537,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
@@ -7181,8 +8548,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
@@ -7190,8 +8559,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
@@ -7199,8 +8570,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
@@ -7208,8 +8581,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
@@ -7217,8 +8592,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
@@ -7226,8 +8603,10 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
@@ -7235,8 +8614,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -7244,8 +8625,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -7253,8 +8636,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -7262,8 +8647,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -7271,8 +8658,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -7280,8 +8669,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -7289,8 +8680,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -7298,8 +8691,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -7307,8 +8702,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -7316,8 +8713,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -7325,8 +8724,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -7334,8 +8735,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -7343,8 +8746,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -7352,8 +8757,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -7361,8 +8768,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -7370,8 +8779,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -7379,8 +8790,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -7388,8 +8801,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -7397,8 +8812,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -7406,8 +8823,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -7415,8 +8834,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -7424,8 +8845,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -7433,8 +8856,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -7442,8 +8867,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -7451,8 +8878,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -7460,8 +8889,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -7469,8 +8900,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -7478,8 +8911,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
@@ -7487,8 +8922,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
@@ -7496,8 +8933,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
@@ -7505,8 +8944,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
@@ -7514,8 +8955,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
@@ -7523,8 +8966,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xd1",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -7532,8 +8977,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xd1",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -7541,8 +8988,10 @@
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xd1",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -7550,8 +8999,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xd3",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -7559,8 +9010,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xd3",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -7568,8 +9021,10 @@
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xd3",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -7577,8 +9032,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xd5",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -7586,8 +9043,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xd5",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -7595,8 +9054,10 @@
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xd5",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -7604,8 +9065,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "Counter": "0,1,2,3",
"EventCode": "0xd7",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
@@ -7613,8 +9076,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "Counter": "0,1,2,3",
"EventCode": "0xd7",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
@@ -7622,8 +9087,10 @@
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "Counter": "0,1,2,3",
"EventCode": "0xd7",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
@@ -7631,24 +9098,30 @@
},
{
"BriefDescription": "UNC_M2P_TxC_CREDITS.PMM",
+ "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_M2P_TxC_CREDITS.PMM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
+ "Counter": "0,1",
"EventCode": "0x2d",
"EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
"UMask": "0x1",
@@ -7656,8 +9129,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
"UMask": "0x10",
@@ -7665,8 +9140,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
"UMask": "0x2",
@@ -7674,8 +9151,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
"UMask": "0x20",
@@ -7683,8 +9162,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
"UMask": "0x4",
@@ -7692,8 +9173,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
"UMask": "0x40",
@@ -7701,8 +9184,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
"UMask": "0x80",
@@ -7710,8 +9195,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
"UMask": "0x8",
@@ -7719,8 +9206,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
"UMask": "0x1",
@@ -7728,8 +9217,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
"UMask": "0x10",
@@ -7737,8 +9228,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
"UMask": "0x2",
@@ -7746,8 +9239,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
"UMask": "0x20",
@@ -7755,8 +9250,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
"UMask": "0x4",
@@ -7764,8 +9261,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
"UMask": "0x40",
@@ -7773,8 +9272,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
"UMask": "0x80",
@@ -7782,8 +9283,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
"UMask": "0x8",
@@ -7791,8 +9294,10 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_TxC_INSERTS.AD_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
"UMask": "0x1",
@@ -7800,8 +9305,10 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_TxC_INSERTS.AD_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
"UMask": "0x10",
@@ -7809,8 +9316,10 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
"UMask": "0x8",
@@ -7818,8 +9327,10 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
"UMask": "0x80",
@@ -7827,8 +9338,10 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_TxC_INSERTS.BL_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
"UMask": "0x4",
@@ -7836,8 +9349,10 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_TxC_INSERTS.BL_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
"UMask": "0x40",
@@ -7845,8 +9360,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa6",
"EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -7854,8 +9371,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa6",
"EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -7863,8 +9382,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa6",
"EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -7872,8 +9393,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa6",
"EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -7881,8 +9404,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa6",
"EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -7890,8 +9415,10 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa6",
"EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -7899,8 +9426,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -7908,8 +9437,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -7917,8 +9448,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -7926,8 +9459,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -7935,8 +9470,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x80",
@@ -7944,8 +9481,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -7953,8 +9492,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -7962,8 +9503,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -7971,8 +9514,10 @@
},
{
"BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
@@ -7980,8 +9525,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -7989,8 +9536,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -7998,8 +9547,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -8007,8 +9558,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -8016,8 +9569,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -8025,8 +9580,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8034,8 +9591,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -8043,8 +9602,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -8052,8 +9613,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -8061,8 +9624,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8070,8 +9635,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -8079,8 +9646,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -8088,8 +9657,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -8097,8 +9668,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -8106,8 +9679,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8115,8 +9690,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -8124,8 +9701,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -8133,8 +9712,10 @@
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -8142,8 +9723,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8151,8 +9734,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -8160,8 +9745,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -8169,8 +9756,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -8178,8 +9767,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -8187,8 +9778,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8196,8 +9789,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -8205,8 +9800,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -8214,8 +9811,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -8223,8 +9822,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8232,8 +9833,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x10",
@@ -8241,8 +9844,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x1",
@@ -8250,8 +9855,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x2",
@@ -8259,8 +9866,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x80",
@@ -8268,8 +9877,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8277,8 +9888,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x40",
@@ -8286,8 +9899,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x4",
@@ -8295,8 +9910,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x8",
@@ -8304,8 +9921,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
@@ -8313,8 +9932,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
@@ -8322,8 +9943,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
@@ -8331,8 +9954,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
@@ -8340,8 +9965,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
@@ -8349,8 +9976,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
@@ -8358,8 +9987,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
@@ -8367,8 +9998,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
@@ -8376,8 +10009,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
@@ -8385,8 +10020,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x1",
@@ -8394,8 +10031,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x1",
@@ -8403,8 +10042,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "Counter": "0,1,2,3",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x2",
@@ -8412,8 +10053,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x80",
@@ -8421,8 +10064,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "Counter": "0,1,2,3",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x4",
@@ -8430,8 +10075,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "Counter": "0,1,2,3",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x4",
@@ -8439,8 +10086,10 @@
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x8",
@@ -8448,8 +10097,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9c",
"EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -8457,8 +10108,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9c",
"EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -8466,8 +10119,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9c",
"EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -8475,8 +10130,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9c",
"EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -8484,8 +10141,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9d",
"EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -8493,8 +10152,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9d",
"EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
@@ -8502,8 +10163,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9d",
"EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -8511,8 +10174,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9d",
"EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x20",
@@ -8520,8 +10185,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9d",
"EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
@@ -8529,8 +10196,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9d",
"EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
@@ -8538,8 +10207,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9d",
"EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
@@ -8547,8 +10218,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9e",
"EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
@@ -8556,8 +10229,10 @@
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9e",
"EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
@@ -8565,8 +10240,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -8574,8 +10251,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -8583,8 +10262,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -8592,8 +10273,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -8601,8 +10284,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -8610,8 +10295,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -8619,8 +10306,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -8628,8 +10317,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -8637,8 +10328,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -8646,8 +10339,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -8655,8 +10350,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -8664,8 +10361,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -8673,8 +10372,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -8682,8 +10383,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -8691,8 +10394,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -8700,8 +10405,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -8709,8 +10416,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -8718,8 +10427,10 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -8727,8 +10438,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -8736,8 +10449,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -8745,8 +10460,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -8754,8 +10471,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -8763,8 +10482,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -8772,8 +10493,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -8781,8 +10504,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -8790,8 +10515,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -8799,8 +10526,10 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -8808,8 +10537,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
@@ -8817,8 +10548,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x10",
@@ -8826,8 +10559,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
@@ -8835,8 +10570,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
@@ -8844,8 +10581,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x4",
@@ -8853,8 +10592,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x40",
@@ -8862,8 +10603,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x8",
@@ -8871,8 +10614,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
@@ -8880,8 +10625,10 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
@@ -8889,8 +10636,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -8898,8 +10647,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
@@ -8907,8 +10658,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -8916,8 +10669,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
@@ -8925,8 +10680,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
@@ -8934,8 +10691,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
@@ -8943,8 +10702,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
@@ -8952,8 +10713,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
@@ -8961,8 +10724,10 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
@@ -8970,8 +10735,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9a",
"EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
@@ -8979,8 +10746,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9a",
"EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x10",
@@ -8988,8 +10757,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9a",
"EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
@@ -8997,8 +10768,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9a",
"EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x20",
@@ -9006,8 +10779,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9a",
"EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
@@ -9015,8 +10790,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9a",
"EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x40",
@@ -9024,8 +10801,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "Counter": "0,1,2,3",
"EventCode": "0x9a",
"EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x8",
@@ -9033,8 +10812,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
@@ -9042,8 +10823,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
@@ -9051,8 +10834,10 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
@@ -9060,8 +10845,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -9069,8 +10856,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -9078,8 +10867,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -9087,8 +10878,10 @@
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -9096,8 +10889,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb4",
"EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -9105,8 +10900,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb4",
"EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -9114,8 +10911,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb4",
"EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -9123,8 +10922,10 @@
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb4",
"EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -9132,8 +10933,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb1",
"EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -9141,8 +10944,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb1",
"EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -9150,8 +10955,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb1",
"EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -9159,8 +10966,10 @@
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb1",
"EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -9168,8 +10977,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb2",
"EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -9177,8 +10988,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb2",
"EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -9186,8 +10999,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb2",
"EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -9195,8 +11010,10 @@
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb2",
"EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
@@ -9204,8 +11021,10 @@
},
{
"BriefDescription": "Vertical IV Ring in Use : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xb3",
"EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
@@ -9213,8 +11032,10 @@
},
{
"BriefDescription": "Vertical IV Ring in Use : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xb3",
"EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
@@ -9222,8 +11043,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb5",
"EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
@@ -9231,8 +11054,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb5",
"EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
@@ -9240,8 +11065,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "Counter": "0,1,2,3",
"EventCode": "0xb5",
"EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
@@ -9249,8 +11076,10 @@
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "Counter": "0,1,2,3",
"EventCode": "0xb5",
"EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
index 814d9599474d..87604c953c0f 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "DRAM Activate Count : All Activates",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M_ACT_COUNT.ALL",
"PerPkg": "1",
@@ -10,8 +11,10 @@
},
{
"BriefDescription": "DRAM Activate Count : Activate due to Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M_ACT_COUNT.BYP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x8",
@@ -19,6 +22,7 @@
},
{
"BriefDescription": "All DRAM CAS commands issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
@@ -28,6 +32,7 @@
},
{
"BriefDescription": "All DRAM read CAS commands issued (including underfills)",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
@@ -37,8 +42,10 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with explicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
"UMask": "0x2",
@@ -46,8 +53,10 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x8",
@@ -55,8 +64,10 @@
},
{
"BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.RD_REG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the total number of DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
"UMask": "0x1",
@@ -64,8 +75,10 @@
},
{
"BriefDescription": "DRAM underfill read CAS commands issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the total of DRAM Read CAS commands issued due to an underfill",
"UMask": "0x4",
@@ -73,6 +86,7 @@
},
{
"BriefDescription": "All DRAM write CAS commands issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
@@ -82,8 +96,10 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x10",
@@ -91,8 +107,10 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.WR_PRE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x20",
@@ -100,28 +118,34 @@
},
{
"BriefDescription": "DRAM Clockticks",
+ "Counter": "0,1,2,3",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Free running counter that increments for the Memory Controller",
+ "Counter": "4",
"EventCode": "0xff",
"EventName": "UNC_M_CLOCKTICKS_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "imc_free_running"
},
{
"BriefDescription": "DRAM Precharge All Commands",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M_DRAM_PRE_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent.",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
@@ -131,6 +155,7 @@
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
"PerPkg": "1",
@@ -140,6 +165,7 @@
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
@@ -149,6 +175,7 @@
},
{
"BriefDescription": "Half clockticks for IMC",
+ "Counter": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_M_HCLOCKTICKS",
"PerPkg": "1",
@@ -156,37 +183,46 @@
},
{
"BriefDescription": "UNC_M_PARITY_ERRORS",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_M_PARITY_ERRORS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_PCLS.RD",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_PCLS.RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_PCLS.TOTAL",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_PCLS.TOTAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_PCLS.WR",
+ "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_PCLS.WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands : All",
+ "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.ALL",
"PerPkg": "1",
@@ -196,22 +232,27 @@
},
{
"BriefDescription": "PMM Commands : Misc Commands (error, flow ACKs)",
+ "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.MISC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands : Misc GNTs",
+ "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.MISC_GNT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands : Reads - RPQ",
+ "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.RD",
"PerPkg": "1",
@@ -221,14 +262,17 @@
},
{
"BriefDescription": "PMM Commands : RPQ GNTs",
+ "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands : Underfill reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.UFILL_RD",
"PerPkg": "1",
@@ -238,14 +282,17 @@
},
{
"BriefDescription": "PMM Commands : Underfill GNTs",
+ "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands : Writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.WR",
"PerPkg": "1",
@@ -255,84 +302,105 @@
},
{
"BriefDescription": "PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding)",
+ "Counter": "0,1,2,3",
"EventCode": "0xEB",
"EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP)",
+ "Counter": "0,1,2,3",
"EventCode": "0xEB",
"EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands - Part 2 : Opportunistic Reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xEB",
"EventName": "UNC_M_PMM_CMD2.OPP_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands - Part 2 : ECC Errors",
+ "Counter": "0,1,2,3",
"EventCode": "0xEB",
"EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands - Part 2 : ERID detectable parity error",
+ "Counter": "0,1,2,3",
"EventCode": "0xEB",
"EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands - Part 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xEB",
"EventName": "UNC_M_PMM_CMD2.PMM_ERID_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xEB",
"EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xEB",
"EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Read Queue Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Read Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Read Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M_PMM_RPQ_INSERTS",
"PerPkg": "1",
@@ -341,6 +409,7 @@
},
{
"BriefDescription": "PMM Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
"PerPkg": "1",
@@ -350,8 +419,10 @@
},
{
"BriefDescription": "PMM Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
"UMask": "0x4",
@@ -359,8 +430,10 @@
},
{
"BriefDescription": "PMM Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
"UMask": "0x2",
@@ -368,34 +441,43 @@
},
{
"BriefDescription": "PMM Write Queue Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Write Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_PMM_WPQ_FLUSH",
+ "Counter": "0,1,2,3",
"EventCode": "0xe8",
"EventName": "UNC_M_PMM_WPQ_FLUSH",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_PMM_WPQ_FLUSH_CYC",
+ "Counter": "0,1,2,3",
"EventCode": "0xe9",
"EventName": "UNC_M_PMM_WPQ_FLUSH_CYC",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Write Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0xE7",
"EventName": "UNC_M_PMM_WPQ_INSERTS",
"PerPkg": "1",
@@ -404,6 +486,7 @@
},
{
"BriefDescription": "PMM Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xE4",
"EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
"PerPkg": "1",
@@ -413,8 +496,10 @@
},
{
"BriefDescription": "PMM Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xE4",
"EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
"UMask": "0x2",
@@ -422,8 +507,10 @@
},
{
"BriefDescription": "PMM Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xE4",
"EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
"UMask": "0x4",
@@ -431,16 +518,20 @@
},
{
"BriefDescription": "Channel PPD Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x1",
@@ -448,8 +539,10 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x2",
@@ -457,8 +550,10 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x4",
@@ -466,8 +561,10 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x8",
@@ -475,8 +572,10 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
"UMask": "0x1",
@@ -484,8 +583,10 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x2",
@@ -493,16 +594,20 @@
},
{
"BriefDescription": "Clock-Enabled Self-Refresh",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
"UMask": "0x1",
@@ -510,8 +615,10 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x2",
@@ -519,6 +626,7 @@
},
{
"BriefDescription": "DRAM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M_PRE_COUNT.ALL",
"PerPkg": "1",
@@ -528,8 +636,10 @@
},
{
"BriefDescription": "DRAM Precharge commands. : Precharge due to page miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests)",
"UMask": "0xc",
@@ -537,6 +647,7 @@
},
{
"BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M_PRE_COUNT.PGT",
"PerPkg": "1",
@@ -546,6 +657,7 @@
},
{
"BriefDescription": "DRAM Precharge commands. : Precharge due to read",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
@@ -555,6 +667,7 @@
},
{
"BriefDescription": "DRAM Precharge commands. : Precharge due to write",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
@@ -564,52 +677,66 @@
},
{
"BriefDescription": "Read Data Buffer Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M_RDB_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Data Buffer Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M_RDB_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Data Buffer Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M_RDB_NOT_EMPTY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Data Buffer Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_M_RDB_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Full Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Full Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
"UMask": "0x1",
@@ -617,8 +744,10 @@
},
{
"BriefDescription": "Read Pending Queue Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
"UMask": "0x2",
@@ -626,6 +755,7 @@
},
{
"BriefDescription": "Read Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS.PCH0",
"PerPkg": "1",
@@ -635,6 +765,7 @@
},
{
"BriefDescription": "Read Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS.PCH1",
"PerPkg": "1",
@@ -644,6 +775,7 @@
},
{
"BriefDescription": "Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
@@ -652,6 +784,7 @@
},
{
"BriefDescription": "Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
@@ -660,749 +793,930 @@
},
{
"BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Accepted",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.ACCEPTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated.",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.FMRD_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated.",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.FMWR_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : Write Accepts",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : Write Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated.",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.NMRD_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated.",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.NMWR_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : FM read completions",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : FM write completions",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : Read Accepts",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : Read Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Rejected",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.REJECTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : NM read completions",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : NM write completions",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": ": Alloc",
+ "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.ALLOC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": ": Dealloc",
+ "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.DEALLOC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.FMTGRWR_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Write Starved",
+ "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.FM_RD_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Write Starved",
+ "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Read Starved",
+ "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.FM_WR_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.NMRD_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.NMWR_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": ": Valid",
+ "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.NM_RD_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read Starved",
+ "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.NM_WR_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": ": Reject",
+ "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.VLD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M_SB_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Cycles Not-Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M_SB_CYCLES_NE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Block region reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Block region writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Persistent Mem reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M_SB_INSERTS.PMM_RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Persistent Mem writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M_SB_INSERTS.PMM_WRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M_SB_INSERTS.RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M_SB_INSERTS.WRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy : Block region reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy : Block region writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy : Persistent Mem reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy : Persistent Mem writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy : Reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M_SB_OCCUPANCY.RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Inserts : All",
+ "Counter": "0,1,2,3",
"EventCode": "0xDA",
"EventName": "UNC_M_SB_PREF_INSERTS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Inserts : DDR4",
+ "Counter": "0,1,2,3",
"EventCode": "0xDA",
"EventName": "UNC_M_SB_PREF_INSERTS.DDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Inserts : Persistent Mem",
+ "Counter": "0,1,2,3",
"EventCode": "0xDA",
"EventName": "UNC_M_SB_PREF_INSERTS.PMM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Occupancy : All",
+ "Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Occupancy : DDR4",
+ "Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_PREF_OCCUPANCY.PMM",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xdb",
"EventName": "UNC_M_SB_PREF_OCCUPANCY.PMEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Mem",
+ "Counter": "0,1,2,3",
"EventCode": "0xdb",
"EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Number of Scoreboard Requests Rejected",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M_SB_REJECT.CANARY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Number of Scoreboard Requests Rejected",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd7",
"EventName": "UNC_M_SB_STRV_ALLOC.FMRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd7",
"EventName": "UNC_M_SB_STRV_ALLOC.FMTGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd7",
"EventName": "UNC_M_SB_STRV_ALLOC.FMWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Read - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M_SB_STRV_ALLOC.FM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read - Clear",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Write - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M_SB_STRV_ALLOC.FM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd7",
"EventName": "UNC_M_SB_STRV_ALLOC.NMRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd7",
"EventName": "UNC_M_SB_STRV_ALLOC.NMWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M_SB_STRV_ALLOC.NM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Write - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M_SB_STRV_ALLOC.NM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xde",
"EventName": "UNC_M_SB_STRV_DEALLOC.FMRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xde",
"EventName": "UNC_M_SB_STRV_DEALLOC.FMTGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xde",
"EventName": "UNC_M_SB_STRV_DEALLOC.FMWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Read - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xDE",
"EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read - Clear",
+ "Counter": "0,1,2,3",
"EventCode": "0xDE",
"EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Write - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xDE",
"EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xde",
"EventName": "UNC_M_SB_STRV_DEALLOC.NMRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xde",
"EventName": "UNC_M_SB_STRV_DEALLOC.NMWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xDE",
"EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Write - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xDE",
"EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd8",
"EventName": "UNC_M_SB_STRV_OCC.FMRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd8",
"EventName": "UNC_M_SB_STRV_OCC.FMTGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd8",
"EventName": "UNC_M_SB_STRV_OCC.FMWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Read",
+ "Counter": "0,1,2,3",
"EventCode": "0xD8",
"EventName": "UNC_M_SB_STRV_OCC.FM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read - Clear",
+ "Counter": "0,1,2,3",
"EventCode": "0xD8",
"EventName": "UNC_M_SB_STRV_OCC.FM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Write",
+ "Counter": "0,1,2,3",
"EventCode": "0xD8",
"EventName": "UNC_M_SB_STRV_OCC.FM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd8",
"EventName": "UNC_M_SB_STRV_OCC.NMRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xd8",
"EventName": "UNC_M_SB_STRV_OCC.NMWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read",
+ "Counter": "0,1,2,3",
"EventCode": "0xD8",
"EventName": "UNC_M_SB_STRV_OCC.NM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Write",
+ "Counter": "0,1,2,3",
"EventCode": "0xD8",
"EventName": "UNC_M_SB_STRV_OCC.NM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
+ "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.NEW",
+ "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.NEW",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.OCC",
+ "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.OCC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
+ "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
+ "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
+ "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
+ "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.RD_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
+ "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.RD_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "2LM Tag Check : Hit in Near Memory Cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M_TAGCHK.HIT",
"PerPkg": "1",
@@ -1411,6 +1725,7 @@
},
{
"BriefDescription": "2LM Tag Check : Miss, no data in this line",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M_TAGCHK.MISS_CLEAN",
"PerPkg": "1",
@@ -1419,6 +1734,7 @@
},
{
"BriefDescription": "2LM Tag Check : Miss, existing data may be evicted to Far Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M_TAGCHK.MISS_DIRTY",
"PerPkg": "1",
@@ -1427,6 +1743,7 @@
},
{
"BriefDescription": "2LM Tag Check : Read Hit in Near Memory Cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M_TAGCHK.NM_RD_HIT",
"PerPkg": "1",
@@ -1435,6 +1752,7 @@
},
{
"BriefDescription": "2LM Tag Check : Write Hit in Near Memory Cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M_TAGCHK.NM_WR_HIT",
"PerPkg": "1",
@@ -1443,24 +1761,30 @@
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
"UMask": "0x1",
@@ -1468,8 +1792,10 @@
},
{
"BriefDescription": "Write Pending Queue Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
"UMask": "0x2",
@@ -1477,6 +1803,7 @@
},
{
"BriefDescription": "Write Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M_WPQ_INSERTS.PCH0",
"PerPkg": "1",
@@ -1486,6 +1813,7 @@
},
{
"BriefDescription": "Write Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M_WPQ_INSERTS.PCH1",
"PerPkg": "1",
@@ -1495,6 +1823,7 @@
},
{
"BriefDescription": "Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
@@ -1503,6 +1832,7 @@
},
{
"BriefDescription": "Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
@@ -1511,8 +1841,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"UMask": "0x1",
@@ -1520,8 +1852,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"UMask": "0x2",
@@ -1529,8 +1863,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"UMask": "0x1",
@@ -1538,8 +1874,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"UMask": "0x2",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
index 920cab6ffe37..03984d61ab29 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Clockticks of the power control unit (PCU)",
+ "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Clockticks of the power control unit (PCU) : The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
@@ -8,147 +9,185 @@
},
{
"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE_TRANSITION_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_DEMOTIONS",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 0 Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 1 Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 2 Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x77",
"EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 3 Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x78",
"EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
"Unit": "PCU"
},
{
"BriefDescription": "AVX256 Frequency Clipping",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_P_FREQ_CLIP_AVX256",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "AVX512 Frequency Clipping",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_P_FREQ_CLIP_AVX512",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
+ "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
+ "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Package C State Residency - C3 : Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
+ "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State : C0 and C1",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Number of cores in C-State : C0 and C1 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"UMask": "0x40",
@@ -156,8 +195,10 @@
},
{
"BriefDescription": "Number of cores in C-State : C3",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Number of cores in C-State : C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"UMask": "0x80",
@@ -165,8 +206,10 @@
},
{
"BriefDescription": "Number of cores in C-State : C6 and C7",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Number of cores in C-State : C6 and C7 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"UMask": "0xc0",
@@ -174,32 +217,40 @@
},
{
"BriefDescription": "External Prochot",
+ "Counter": "0,1,2,3",
"EventCode": "0x0A",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
+ "Counter": "0,1,2,3",
"EventCode": "0x09",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
"BriefDescription": "VR Hot",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
"Unit": "PCU"
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
index e3227c7f2fe9..9df790d4361f 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
@@ -18,6 +20,7 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -26,6 +29,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -34,6 +38,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -42,6 +47,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -50,6 +56,7 @@
},
{
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
@@ -58,6 +65,7 @@
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
@@ -66,6 +74,7 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
@@ -75,6 +84,7 @@
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -83,6 +93,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -91,6 +102,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -99,6 +111,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -107,6 +120,7 @@
},
{
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
@@ -115,6 +129,7 @@
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
@@ -123,6 +138,7 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
@@ -132,6 +148,7 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -140,6 +157,7 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -148,6 +166,7 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -156,6 +175,7 @@
},
{
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
@@ -164,6 +184,7 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
+ "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -172,6 +193,7 @@
},
{
"BriefDescription": "STLB flush attempts",
+ "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index bb16463d9701..9056784e23f7 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -15,7 +15,7 @@ GenuineIntel-6-A[DE],v1.02,graniterapids,core
GenuineIntel-6-(3C|45|46),v35,haswell,core
GenuineIntel-6-3F,v28,haswellx,core
GenuineIntel-6-7[DE],v1.22,icelake,core
-GenuineIntel-6-6[AC],v1.24,icelakex,core
+GenuineIntel-6-6[AC],v1.26,icelakex,core
GenuineIntel-6-3A,v24,ivybridge,core
GenuineIntel-6-3E,v24,ivytown,core
GenuineIntel-6-2D,v24,jaketown,core
--
2.45.2.627.g7a2c4fd464-goog
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