linux-kernel - Re: [RESEND PATCH 05/12] perf/x86: Add config

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Message-ID: <20240620074402.GS31592@noisy.programming.kicks-ass.net>
Date: Thu, 20 Jun 2024 09:44:02 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: kan.liang@...ux.intel.com
Cc: mingo@...nel.org, acme@...nel.org, namhyung@...nel.org,
	irogers@...gle.com, adrian.hunter@...el.com,
	alexander.shishkin@...ux.intel.com, linux-kernel@...r.kernel.org,
	ak@...ux.intel.com, eranian@...gle.com,
	Dapeng Mi <dapeng1.mi@...ux.intel.com>
Subject: Re: [RESEND PATCH 05/12] perf/x86: Add config_mask to represent
 EVENTSEL bitmask

On Tue, Jun 18, 2024 at 08:10:37AM -0700, kan.liang@...ux.intel.com wrote:
> From: Kan Liang <kan.liang@...ux.intel.com>
> 
> Different vendors may support different fields in EVENTSEL MSR, such as
> Intel would introduce new fields umask2 and eq bits in EVENTSEL MSR
> since Perfmon version 6. However, a fixed mask X86_RAW_EVENT_MASK is
> used to filter the attr.config.
> 

> @@ -1231,6 +1233,11 @@ static inline int x86_pmu_num_counters_fixed(struct pmu *pmu)
>  	return hweight64(hybrid(pmu, fixed_cntr_mask64));
>  }
>  
> +static inline u64 x86_pmu_get_event_config(struct perf_event *event)
> +{
> +	return event->attr.config & hybrid(event->pmu, config_mask);
> +}

Seriously, we're going to be having such major event encoding
differences between cores on a single chip?