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Message-ID: <CAC=S1njt1tEH-S2YYKvewRmqta468DuteZFCXKgC02vMUoiBdA@mail.gmail.com>
Date: Thu, 20 Jun 2024 16:49:16 +0800
From: Fei Shao <fshao@...omium.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: krzk+dt@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
robh@...nel.org, conor+dt@...nel.org, matthias.bgg@...il.com,
jassisinghbrar@...il.com, garmin.chang@...iatek.com, houlong.wei@...iatek.com,
Jason-ch.Chen@...iatek.com, amergnat@...libre.com, Elvis.Wang@...iatek.com,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, kernel@...labora.com
Subject: Re: [PATCH 1/3] arm64: dts: mediatek: mt8188: Fix VPPSYS0/1 node name/compatibles
On Wed, Jun 19, 2024 at 4:53 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com> wrote:
>
> Like VDOSYS0/1, the VPPSYS0 and VPPSYS1 are syscon nodes, as
> described by the mediatek,mmsys binding: fix the node name to
> be syscon@...ress and add "syscon" to the list of compatible
> strings for both VPPSYS0 and VPPSYS1.
>
> Fixes: 9461e0caac9e ("arm64: dts: Add MediaTek MT8188 dts and evaluation board and Makefile")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: Fei Shao <fshao@...omium.org>
> ---
> arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index 3b02170562ae..77c4f2d104cd 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -1331,8 +1331,8 @@ mfgcfg: clock-controller@...bf000 {
> #clock-cells = <1>;
> };
>
> - vppsys0: clock-controller@...00000 {
> - compatible = "mediatek,mt8188-vppsys0";
> + vppsys0: syscon@...00000 {
> + compatible = "mediatek,mt8188-vppsys0", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> #clock-cells = <1>;
> };
> @@ -1349,8 +1349,8 @@ wpesys_vpp0: clock-controller@...02000 {
> #clock-cells = <1>;
> };
>
> - vppsys1: clock-controller@...00000 {
> - compatible = "mediatek,mt8188-vppsys1";
> + vppsys1: syscon@...00000 {
> + compatible = "mediatek,mt8188-vppsys1", "syscon";
> reg = <0 0x14f00000 0 0x1000>;
> #clock-cells = <1>;
> };
> --
> 2.45.2
>
>
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