linux-kernel - Re: [PATCH v3 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree

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Message-ID: <CAGb2v64ZuLhnZn4G_Zbqqosh46Fh57WtXCcCFkwMA2phtLzq1g@mail.gmail.com>
Date: Thu, 20 Jun 2024 18:06:56 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Charlie Jenkins <charlie@...osinc.com>
Cc: Conor Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Jisheng Zhang <jszhang@...nel.org>, Jernej Skrabec <jernej.skrabec@...il.com>, 
	Samuel Holland <samuel@...lland.org>, Jonathan Corbet <corbet@....net>, Shuah Khan <shuah@...nel.org>, 
	Guo Ren <guoren@...nel.org>, Evan Green <evan@...osinc.com>, Andy Chiu <andy.chiu@...ive.com>, 
	Jessica Clarke <jrtc27@...c27.com>, linux-riscv@...ts.infradead.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-sunxi@...ts.linux.dev, linux-doc@...r.kernel.org, 
	linux-kselftest@...r.kernel.org, Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v3 03/13] riscv: dts: allwinner: Add xtheadvector to the
 D1/D1s devicetree

On Thu, Jun 20, 2024 at 7:57 AM Charlie Jenkins <charlie@...osinc.com> wrote:
>
> The D1/D1s SoCs support xtheadvector so it can be included in the
> devicetree. Also include vlenb for the cpu.
>
> Signed-off-by: Charlie Jenkins <charlie@...osinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Acked-by: Chen-Yu Tsai <wens@...e.org>

If the RISC-V maintainers want to take the whole series.

> ---
>  arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 64c3c2e6cbe0..6367112e614a 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -27,7 +27,8 @@ cpu0: cpu@0 {
>                         riscv,isa = "rv64imafdc";
>                         riscv,isa-base = "rv64i";
>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> -                                              "zifencei", "zihpm";
> +                                              "zifencei", "zihpm", "xtheadvector";
> +                       thead,vlenb = <128>;
>                         #cooling-cells = <2>;
>
>                         cpu0_intc: interrupt-controller {
>
> --
> 2.34.1
>