Date: Fri, 21 Jun 2024 18:59:59 +0100
From: Jessica Clarke <jrtc27@...c27.com>
To: Yunhui Cui <cuiyunhui@...edance.com>,
 Palmer Dabbelt <palmer@...belt.com>
Cc: Jonathan Corbet <corbet@....net>,
 Paul Walmsley <paul.walmsley@...ive.com>,
 Albert Ou <aou@...s.berkeley.edu>,
 Clément Léger <cleger@...osinc.com>,
 Evan Green <evan@...osinc.com>,
 Conor Dooley <conor.dooley@...rochip.com>,
 costa.shul@...hat.com,
 Andy Chiu <andy.chiu@...ive.com>,
 samitolvanen@...gle.com,
 linux-doc@...r.kernel.org,
 linux-riscv <linux-riscv@...ts.infradead.org>,
 LKML <linux-kernel@...r.kernel.org>,
 Palmer Dabbelt <palmer@...osinc.com>
Subject: Re: [PATCH v2] RISC-V: Provide the frequency of time CSR via hwprobe

On 21 Jun 2024, at 12:31, Yunhui Cui <cuiyunhui@...edance.com> wrote:
> 
> From: Palmer Dabbelt <palmer@...osinc.com>
> 
> A handful of user-visible behavior is based on the frequency of the
> time CSR.
> 
> Signed-off-by: Palmer Dabbelt <palmer@...osinc.com>
> Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>
> ---
> Documentation/arch/riscv/hwprobe.rst  | 2 ++
> arch/riscv/include/asm/hwprobe.h      | 2 +-
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c       | 5 +++++
> 4 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index fc015b452ebf..c07f159d8906 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -229,3 +229,5 @@ The following keys are defined:
> 
> * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
>   represents the size of the Zicboz block in bytes.
> +
> +* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `mtime`.

This still says mtime.

Jess

> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 630507dff5ea..150a9877b0af 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -8,7 +8,7 @@
> 
> #include <uapi/asm/hwprobe.h>
> 
> -#define RISCV_HWPROBE_MAX_KEY 6
> +#define RISCV_HWPROBE_MAX_KEY 7
> 
> static inline bool riscv_hwprobe_key_is_valid(__s64 key)
> {
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 7b95fadbea2a..18754341ff14 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -73,6 +73,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
> #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
> #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
> +#define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 7
> /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
> 
> /* Flags */
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 83fcc939df67..fc3b40fb9def 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -8,6 +8,7 @@
> #include <asm/cacheflush.h>
> #include <asm/cpufeature.h>
> #include <asm/hwprobe.h>
> +#include <asm/delay.h>
> #include <asm/sbi.h>
> #include <asm/switch_to.h>
> #include <asm/uaccess.h>
> @@ -226,6 +227,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> pair->value = riscv_cboz_block_size;
> break;
> 
> + case RISCV_HWPROBE_KEY_TIME_CSR_FREQ:
> + pair->value = riscv_timebase;
> + break;
> +
> /*
> * For forward compatibility, unknown keys don't fail the whole
> * call, but get their element key set to -1 and value set to 0
> -- 
> 2.20.1
> 
> 
> _______________________________________________
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