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Message-ID: <87plsam4dq.ffs@tglx>
Date: Fri, 21 Jun 2024 22:23:45 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Aleksandar Rikalo <aleksandar.rikalo@...mia.com>, Thomas Bogendoerfer
<tsbogend@...ha.franken.de>
Cc: Aleksandar Rikalo <arikalo@...il.com>, Chao-ying Fu <cfu@...ecomp.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>, Geert Uytterhoeven
<geert@...ux-m68k.org>, Greg Ungerer <gerg@...nel.org>, Hauke Mehrtens
<hauke@...ke-m.de>, Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>, Jiaxun
Yang <jiaxun.yang@...goat.com>, linux-kernel@...r.kernel.org,
linux-mips@...r.kernel.org, Marc Zyngier <maz@...nel.org>, Paul Burton
<paulburton@...nel.org>, Peter Zijlstra <peterz@...radead.org>, Serge
Semin <fancer.lancer@...il.com>, Tiezhu Yang <yangtiezhu@...ngson.cn>
Subject: Re: [PATCH v4 05/14] irqchip: mips-gic: Setup defaults in each cluster
On Sat, May 11 2024 at 12:43, Aleksandar Rikalo wrote:
> From: Chao-ying Fu <cfu@...ecomp.com>
>
> In multi-cluster MIPS I6500 systems we have a GIC per cluster. The
> default shared interrupt setup that we configure in gic_of_init() will
> only apply to the GIC in the cluster containing the boot CPU, leaving
> the GICs of other clusters unconfigured. Similarly configure other
> clusters here.
We ...
> + nclusters = mips_cps_numclusters();
> + for (cl = 0; cl < nclusters; cl++) {
> + if (cl == cpu_cluster(¤t_cpu_data)) {
> + for (i = 0; i < gic_shared_intrs; i++) {
> + change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
> + change_gic_trig(i, GIC_TRIG_LEVEL);
> + write_gic_rmask(i);
> + }
> + } else {
> + mips_cm_lock_other(cl, 0, 0,
> + CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
Please get rid of these line breaks. You have 100 characters available.
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