linux-kernel - Re: [External] Re: [PATCH] RISC-V: Provide the frequency of mtime via hwprobe

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Message-ID: <8fac6e0f11ab5f5fc28be6e73f196b38e99f8c39.camel@icenowy.me>
Date: Fri, 21 Jun 2024 13:18:22 +0800
From: Icenowy Zheng <uwu@...nowy.me>
To: yunhui cui <cuiyunhui@...edance.com>
Cc: Jessica Clarke <jrtc27@...c27.com>, Jonathan Corbet <corbet@....net>, 
 Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt
 <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Clément Léger <cleger@...osinc.com>, Evan Green
 <evan@...osinc.com>, Conor Dooley <conor.dooley@...rochip.com>,
 costa.shul@...hat.com, Andy Chiu <andy.chiu@...ive.com>,
 samitolvanen@...gle.com, linux-doc@...r.kernel.org,  linux-riscv
 <linux-riscv@...ts.infradead.org>, LKML <linux-kernel@...r.kernel.org>,
 Palmer Dabbelt <palmer@...osinc.com>
Subject: Re: [External] Re: [PATCH] RISC-V: Provide the frequency of mtime
 via hwprobe

在 2024-06-21星期五的 11:01 +0800，yunhui cui写道：
> Hi Icenowy,
> 
> On Wed, Jun 19, 2024 at 7:51 AM Icenowy Zheng <uwu@...nowy.me> wrote:
> > 
> > 在 2024-06-18星期二的 18:11 +0100，Jessica Clarke写道：
> > > On 18 Jun 2024, at 12:46, Yunhui Cui <cuiyunhui@...edance.com>
> > > wrote:
> > > > 
> > > > From: Palmer Dabbelt <palmer@...osinc.com>
> > > > 
> > > > A handful of user-visible behavior is based on the frequency of
> > > > the
> > > > machine-mode time.
> > > > 
> > > > Signed-off-by: Palmer Dabbelt <palmer@...osinc.com>
> > > > Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>
> > > 
> > > I would suggest referring to the user-mode CSR instead, i.e.
> > > “time”
> > > rather than “mtime” throughout in names and descriptions, since
> > > that’s
> > > the thing that user-mode software is actually reading from.
> > 
> > Agree. MTIME isn't even a thing defined in RISC-V ISA -- it's part
> > of
> > the ACLINT timer spec, but before ACLINT gets widely accepted, it's
> > just some SiFive thing that got copied by many other vendors (and
> > vendors such as T-Head even provides CLINT w/o MTIME register (well
> > because these T-Head cores have reference source code available,
> > this
> > is because of their CPU design uses an external counter fed as TIME
> > register)).
> 
> Okay, Thanks for your suggestions,  I think this modification is more
> appropriate:
> 
> RISC-V: Provide the frequency of time counter via hwprobe

Sure, or you could just say time CSR, which is a defined CSR in the
user ISA document, and allow to be read from userspace.

> 
> A handful of user-visible behavior is based on the frequency of the
> time counter.
> 
> What do you think ?
> 
> > 
> > > 
> > > Jess
> > > 
> > > 
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@...ts.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> > 
> 
> Thanks,
> Yunhui

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