| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <c3e2e7a1-e424-4808-a690-a457e0526f3f@kernel.org>
Date: Fri, 21 Jun 2024 12:02:31 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: gchan9527@...il.com, Robert Foss <rfoss@...nel.org>,
Todor Tomov <todor.too@...il.com>,
Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, cros-qcom-dts-watchers@...omium.org,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>
Cc: linux-media@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/6] media: dt-bindings: media: camss: Add
qcom,sc7180-camss binding
On 21/06/2024 11:40, George Chan via B4 Relay wrote:
> From: George Chan <gchan9527@...il.com>
>
> Add bindings for qcom,sc7180-camss in order to support the camera
> subsystem for sm7125 as found in the Xiaomi Redmi 9 Pro cellphone.
>
> Signed-off-by: George Chan <gchan9527@...il.com>
Subject: just one media (first). No need to write media: media: ...
A nit, subject: drop second/last, redundant "binding". The "dt-bindings"
prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
> ---
> .../bindings/media/qcom,sc7180-camss.yaml | 324 +++++++++++++++++++++
> 1 file changed, 324 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-camss.yaml
> new file mode 100644
> index 000000000000..4dc10c32ee9c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-camss.yaml
> @@ -0,0 +1,324 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sc7180-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm CAMSS ISP
What is CAMSS?
> +
> +maintainers:
> + - Robert Foss <robert.foss@...aro.org>
For sure this is not true. Robert does not work in Linaro and I doubt he
cares that much about camss.
> +
> +description: |
Do not need '|' unless you need to preserve formatting.
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
> +
> +properties:
> + compatible:
> + const: qcom,sc7180-camss
> +
> + clocks:
> + minItems: 25
Drop minItems
> + maxItems: 25
> +
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: cpas_ahb
> + - const: cphy_rx_src
> + - const: csi0
> + - const: csi1
> + - const: csi2
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: gcc_camera_ahb
> + - const: gcc_camera_axi
> + - const: soc_ahb
> + - const: vfe0_axi
> + - const: vfe0
> + - const: vfe0_cphy_rx
> + - const: vfe1_axi
> + - const: vfe1
> + - const: vfe1_cphy_rx
> + - const: vfe_lite
> + - const: vfe_lite_cphy_rx
> +
> + interrupts:
> + minItems: 10
Drop minItems
> + maxItems: 10
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: vfe0
> + - const: vfe1
> + - const: vfe_lite
> +
> + iommus:
> + maxItems: 4
> +
> + power-domains:
> + items:
> + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + reg:
> + minItems: 10
Drop minItems
> + maxItems: 10
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: vfe0
> + - const: vfe1
> + - const: vfe_lite
> +
> + vdda-phy-supply:
> + description:
> + Phandle to a regulator supply to PHY core block.
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> +required:
> + - clock-names
> + - clocks
> + - compatible
Keep the list ordered, the same as list properties.
> + - interrupt-names
> + - interrupts
> + - iommus
> + - power-domains
> + - reg
> + - reg-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,camcc-sc7180.h>
> + #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss: camss@...3000 {
> + compatible = "qcom,sc7180-camss";
> +
> + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
Missed alignment with previous <.
> + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY0_CLK>,
> + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY1_CLK>,
> + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY2_CLK>,
> + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY3_CLK>,
> + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&clock_camcc CAM_CC_SOC_AHB_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>;
> +
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
Same problem.
> + "csi0",
> + "csi1",
> + "csi2",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "gcc_camera_ahb",
> + "gcc_camera_axi",
> + "soc_ahb",
> + "vfe0_axi",
> + "vfe0",
> + "vfe0_cphy_rx",
> + "vfe1_axi",
> + "vfe1",
> + "vfe1_cphy_rx",
> + "vfe_lite",
> + "vfe_lite_cphy_rx";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "vfe0",
> + "vfe1",
> + "vfe_lite";
> +
> + iommus = <&apps_smmu 0x820 0x0>,
> + <&apps_smmu 0x840 0x0>,
> + <&apps_smmu 0x860 0x0>;
> +
> + power-domains = <&camcc IFE_0_GDSC>,
> + <&camcc IFE_1_GDSC>,
> + <&camcc TITAN_TOP_GDSC>;
> +
> + reg = <0 0xacb3000 0 0x1000>,
reg is always the second property. See DTS coding style.
> + <0 0xacba000 0 0x1000>,
> + <0 0xacc8000 0 0x1000>,
> + <0 0xac65000 0 0x1000>,
> + <0 0xac66000 0 0x1000>,
> + <0 0xac67000 0 0x1000>,
> + <0 0xac68000 0 0x1000>,
> + <0 0xacaf000 0 0x4000>,
> + <0 0xacb6000 0 0x4000>,
> + <0 0xacc4000 0 0x4000>;
> +
> + reg-names = "csid0",
So this will be the third property.
Best regards,
Krzysztof
Powered by blists - more mailing lists