linux-kernel - Re: [PATCH v1 5/7] clk: qcom: gcc-ipq9574: Add CPR clock definition

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Message-ID: <ZnVh5d8RfPnMBvN8@hu-varada-blr.qualcomm.com>
Date: Fri, 21 Jun 2024 16:50:05 +0530
From: Varadarajan Narayanan <quic_varada@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <angelogioacchino.delregno@...labora.com>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <ulf.hansson@...aro.org>, <quic_sibis@...cinc.com>,
        <quic_rjendra@...cinc.com>, <luca@...tu.xyz>, <abel.vesa@...aro.org>,
        <quic_rohiagar@...cinc.com>, <danila@...xyga.com>,
        <otto.pflueger@...cue.de>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <linux-pm@...r.kernel.org>
Subject: Re: [PATCH v1 5/7] clk: qcom: gcc-ipq9574: Add CPR clock definition

On Thu, Jun 20, 2024 at 06:11:32PM +0300, Dmitry Baryshkov wrote:
> On Thu, Jun 20, 2024 at 01:44:25PM GMT, Varadarajan Narayanan wrote:
> > Add the CPR clock definition needed for enabling access to
> > CPR register space.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> > ---
> >  drivers/clk/qcom/gcc-ipq9574.c | 38 ++++++++++++++++++++++++++++++++++
> >  1 file changed, 38 insertions(+)
> >
> > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> > index e1dc74d04ed1..7c8eb94f654b 100644
> > --- a/drivers/clk/qcom/gcc-ipq9574.c
> > +++ b/drivers/clk/qcom/gcc-ipq9574.c
> > @@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = {
> >  	},
> >  };
> >
> > +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
> > +	F(24000000, P_XO, 1, 0, 0),
> > +	{ }
> > +};
> > +
> > +static struct clk_rcg2 rbcpr_clk_src = {
> > +	.cmd_rcgr = 0x48044,
> > +	.mnd_width = 0,
> > +	.hid_width = 5,
> > +	.parent_map = gcc_xo_map,
> > +	.freq_tbl = ftbl_gp1_clk_src,
> > +	.clkr.hw.init = &(struct clk_init_data){
> > +		.name = "rbcpr_clk_src",
> > +		.parent_data = gcc_xo_gpll0_gpll4,
> > +		.num_parents = ARRAY_SIZE(gcc_xo_map),
> > +		.ops = &clk_rcg2_ops,
> > +	},
> > +};
> > +
> > +static struct clk_branch gcc_rbcpr_clk = {
> > +	.halt_reg = 0x48008,
> > +	.halt_check = BRANCH_HALT,
> > +	.clkr = {
> > +		.enable_reg = 0x48008,
> > +		.enable_mask = BIT(0),
> > +		.hw.init = &(struct clk_init_data){
> > +			.name = "gcc_rbcpr_clk",
> > +			.parent_hws = (const struct clk_hw *[]) {
> > +				&rbcpr_clk_src.clkr.hw,
>
> Where is the &rbcpr_clk_src registered?

Oops. Missed it. Will post a corrected patch.

Thanks
Varada

> > +			},
> > +			.num_parents = 1,
> > +			.flags = CLK_SET_RATE_PARENT,
> > +			.ops = &clk_branch2_ops,
> > +		},
> > +	},
> > +};
> > +
> >  static struct clk_hw *gcc_ipq9574_hws[] = {
> >  	&gpll0_out_main_div2.hw,
> >  	&gcc_xo_div4_clk_src.hw,
> > @@ -4219,6 +4256,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
> >  	[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
> >  	[GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
> >  	[GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
> > +	[GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr,
> >  };
> >
> >  static const struct qcom_reset_map gcc_ipq9574_resets[] = {
> > --
> > 2.34.1