| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20240623120026.44198-3-krzysztof.kozlowski@linaro.org>
Date: Sun, 23 Jun 2024 14:00:26 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Rob Clark <robdclark@...il.com>,
Sean Paul <sean@...rly.run>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH 3/3] dt-bindings: display/msm/gpu: constrain reg/reg-names per variant
MMIO address space is known per each variant of Adreno GPU, so we can
constrain the reg/reg-names entries for each variant. There is no DTS
for A619, so that part is not accurate but could be corrected later.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
.../devicetree/bindings/display/msm/gpu.yaml | 87 +++++++++++++++++--
1 file changed, 79 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index baea1946c65d..e83f13123fc9 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -130,6 +130,22 @@ required:
additionalProperties: false
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
+ then:
+ properties:
+ reg:
+ minItems: 3
+
+ reg-names:
+ items:
+ - const: kgsl_3d0_reg_memory
+ - const: cx_mem
+ - const: cx_dbgc
+
- if:
properties:
compatible:
@@ -164,6 +180,13 @@ allOf:
minItems: 2
maxItems: 7
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: kgsl_3d0_reg_memory
+
required:
- clocks
- clock-names
@@ -196,11 +219,12 @@ allOf:
- const: xo
description: GPUCC clocksource clock
+ reg:
+ maxItems: 1
+
reg-names:
- minItems: 1
items:
- const: kgsl_3d0_reg_memory
- - const: cx_dbgc
required:
- clocks
@@ -217,12 +241,59 @@ allOf:
clocks: false
clock-names: false
- reg-names:
- minItems: 1
- items:
- - const: kgsl_3d0_reg_memory
- - const: cx_mem
- - const: cx_dbgc
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,adreno-640.1
+ - qcom,adreno-680.1
+ then:
+ properties:
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: kgsl_3d0_reg_memory
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,adreno-619.0
+ - qcom,adreno-630.2
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: kgsl_3d0_reg_memory
+ - const: cx_mem
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,adreno-618.0
+ - qcom,adreno-635.0
+ - qcom,adreno-690.0
+ - qcom,adreno-730.1
+ then:
+ properties:
+ reg:
+ minItems: 3
+
+ reg-names:
+ items:
+ - const: kgsl_3d0_reg_memory
+ - const: cx_mem
+ - const: cx_dbgc
examples:
- |
--
2.43.0
Powered by blists - more mailing lists