lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [day] [month] [year] [list]
Message-ID: <171915662884.10875.17342495395410962795.tip-bot2@tip-bot2>
Date: Sun, 23 Jun 2024 15:30:28 -0000
From: tip-bot2 for Pali Rohár <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: pali@...nel.org, kabel@...nel.org, Thomas Gleixner <tglx@...utronix.de>,
 Andrew Lunn <andrew@...n.ch>, x86@...nel.org, linux-kernel@...r.kernel.org,
 maz@...nel.org
Subject: [tip: irq/core] irqchip/armada-370-xp: Only call ipi_resume() if IPI
 is available

The following commit has been merged into the irq/core branch of tip:

Commit-ID:     de796fc184179de86fb87f94178459b5b20b1b1b
Gitweb:        https://git.kernel.org/tip/de796fc184179de86fb87f94178459b5b20b1b1b
Author:        Pali Rohár <pali@...nel.org>
AuthorDate:    Fri, 21 Jun 2024 11:38:29 +02:00
Committer:     Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Sun, 23 Jun 2024 17:23:08 +02:00

irqchip/armada-370-xp: Only call ipi_resume() if IPI is available

IPI is available only on systems where the mpic controller does not have a
parent interrupt defined (e.g. on Armada XP). If a parent interrupt is
defined, inter-processor interrupts are handled by an interrupt controller
higher in the hierarchy (most probably a parent GIC).

Only call ipi_resume() on systems where IPI is available in the mpic
controller.

Signed-off-by: Pali Rohár <pali@...nel.org>
Signed-off-by: Marek Behún <kabel@...nel.org>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Andrew Lunn <andrew@...n.ch>

[ refactored a little and changed commit message ]
---
 drivers/irqchip/irq-armada-370-xp.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 526077d..deb4c9b 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -29,6 +29,7 @@
 #include <linux/slab.h>
 #include <linux/syscore_ops.h>
 #include <linux/msi.h>
+#include <linux/types.h>
 #include <asm/mach/arch.h>
 #include <asm/exception.h>
 #include <asm/smp_plat.h>
@@ -156,6 +157,17 @@ static DEFINE_MUTEX(msi_used_lock);
 static phys_addr_t msi_doorbell_addr;
 #endif
 
+static inline bool is_ipi_available(void)
+{
+	/*
+	 * We distinguish IPI availability in the IC by the IC not having a
+	 * parent irq defined. If a parent irq is defined, there is a parent
+	 * interrupt controller (e.g. GIC) that takes care of inter-processor
+	 * interrupts.
+	 */
+	return parent_irq <= 0;
+}
+
 static inline bool is_percpu_irq(irq_hw_number_t irq)
 {
 	if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
@@ -521,7 +533,8 @@ static void armada_xp_mpic_reenable_percpu(void)
 		armada_370_xp_irq_unmask(data);
 	}
 
-	ipi_resume();
+	if (is_ipi_available())
+		ipi_resume();
 
 	armada_370_xp_msi_reenable_percpu();
 }
@@ -744,7 +757,8 @@ static void armada_370_xp_mpic_resume(void)
 	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
 		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 
-	ipi_resume();
+	if (is_ipi_available())
+		ipi_resume();
 }
 
 static struct syscore_ops armada_370_xp_mpic_syscore_ops = {

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ