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Message-ID: <ecc5fbd0-52e1-443f-8e5a-2546328319b2@amd.com>
Date: Mon, 24 Jun 2024 12:56:29 -0500
From: Terry Bowman <Terry.Bowman@....com>
To: Dan Williams <dan.j.williams@...el.com>, ira.weiny@...el.com,
dave@...olabs.net, dave.jiang@...el.com, alison.schofield@...el.com,
ming4.li@...el.com, vishal.l.verma@...el.com, jim.harris@...sung.com,
ilpo.jarvinen@...ux.intel.com, ardb@...nel.org,
sathyanarayanan.kuppuswamy@...ux.intel.com, linux-cxl@...r.kernel.org,
linux-kernel@...r.kernel.org, Yazen.Ghannam@....com, Robert.Richter@....com
Cc: Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org
Subject: Re: [RFC PATCH 1/9] PCI/AER: Update AER driver to call root port and
downstream port UCE handlers
Hi Dan,
I added a response below.
On 6/21/24 14:17, Dan Williams wrote:
> Terry Bowman wrote:
>> The AER service driver does not currently call a handler for AER
>> uncorrectable errors (UCE) detected in root ports or downstream
>> ports. This is not needed in most cases because common PCIe port
>> functionality is handled by portdrv service drivers.
>>
>> CXL root ports include CXL specific RAS registers that need logging
>> before starting do_recovery() in the UCE case.
>>
>> Update the AER service driver to call the UCE handler for root ports
>> and downstream ports. These PCIe port devices are bound to the portdrv
>> driver that includes a CE and UCE handler to be called.
>>
>> Signed-off-by: Terry Bowman <terry.bowman@....com>
>> Cc: Bjorn Helgaas <bhelgaas@...gle.com>
>> Cc: linux-pci@...r.kernel.org
>> ---
>> drivers/pci/pcie/err.c | 20 ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>>
>> diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c
>> index 705893b5f7b0..a4db474b2be5 100644
>> --- a/drivers/pci/pcie/err.c
>> +++ b/drivers/pci/pcie/err.c
>> @@ -203,6 +203,26 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
>> pci_ers_result_t status = PCI_ERS_RESULT_CAN_RECOVER;
>> struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
>>
>> + /*
>> + * PCIe ports may include functionality beyond the standard
>> + * extended port capabilities. This may present a need to log and
>> + * handle errors not addressed in this driver. Examples are CXL
>> + * root ports and CXL downstream switch ports using AER UIE to
>> + * indicate CXL UCE RAS protocol errors.
>> + */
>> + if (type == PCI_EXP_TYPE_ROOT_PORT ||
>> + type == PCI_EXP_TYPE_DOWNSTREAM) {
>> + struct pci_driver *pdrv = dev->driver;
>> +
>> + if (pdrv && pdrv->err_handler &&
>> + pdrv->err_handler->error_detected) {
>> + const struct pci_error_handlers *err_handler;
>> +
>> + err_handler = pdrv->err_handler;
>> + status = err_handler->error_detected(dev, state);
>> + }
>> + }
>> +
>
> Would not a more appropriate place for this be pci_walk_bridge() where
> the ->subordinate == NULL and these type-check cases are unified?
It does. I can take a look at moving that.
Regards,
Terry
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