linux-kernel - Re: [PATCH v4 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date: Mon, 24 Jun 2024 13:38:58 -0600
From: "Rob Herring (Arm)" <robh@...nel.org>
To: daire.mcnamara@...rochip.com
Cc: linux-kernel@...r.kernel.org, conor.dooley@...rochip.com, kw@...ux.com,
	krzk+dt@...nel.org, devicetree@...r.kernel.org,
	lpieralisi@...nel.org, bhelgaas@...gle.com,
	linux-pci@...r.kernel.org, conor+dt@...nel.org,
	linux-riscv@...ts.infradead.org, ilpo.jarvinen@...ux.intel.com
Subject: Re: [PATCH v4 3/3] dt-bindings: PCI: microchip,pcie-host: allow
 dma-noncoherent


On Fri, 21 Jun 2024 12:29:15 +0100, daire.mcnamara@...rochip.com wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> PolarFire SoC may be configured in a way that requires non-coherent DMA
> handling. On RISC-V, buses are coherent by default & the dma-noncoherent
> property is required to denote buses or devices that are non-coherent.
> 
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> Signed-off-by: Daire McNamara <daire.mcnamara@...rochip.com>
> ---
>  Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@...nel.org>