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Date: Mon, 24 Jun 2024 08:01:05 +0000
From: Zhou Shengqing <zhoushengqing@...info.com>
To: Bjorn Helgaas <bhelgaas@...gle.com>,
	Dave Hansen <dave.hansen@...ux.intel.com>
Cc: linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	x86@...nel.org,
	zhoushengqing@...info.com
Subject: Re: Re: [PATCH] PCI: Enable io space 1k granularity for intel cpu root port

> > That seems like a really broken kind of encapsulation.  I'd be
> > surprised if there were not a bit in each of those Root Ports that
> > indicates this.

> Your understanding is completely correct.intel ICX SPR RMR (even GNR) 
> CPU EDS Vol2(register) spec says "This bit when set, enables 1K granularity
> for I/O space decode in each of the virtual P2P bridges corresponding to 
> root ports,and DMI ports." it targets all P2P bridges within the same root bus,
> not the root port itself.The root ports configuration space doesn't have a 
> "EN1K" bit. 

For this reason, it doesn't seem feasible to implement this patch in 
fixup.c or quirks.c.Would it be reasonable to implement this patch in the 
pcibios_fixup_bus function in /x86/pci/common.c? I also think adding this patch
in pci/probe.c is not a good idea.

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