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Message-Id: <20240624081906.1399447-3-jacobe.zang@wesion.com>
Date: Mon, 24 Jun 2024 16:19:03 +0800
From: Jacobe Zang <jacobe.zang@...ion.com>
To: arend.vanspriel@...adcom.com
Cc: kvalo@...nel.org,
duoming@....edu.cn,
bhelgaas@...gle.com,
minipli@...ecurity.net,
linux-wireless@...r.kernel.org,
brcm80211@...ts.linux.dev,
brcm80211-dev-list.pdl@...adcom.com,
megi@....cz,
robh@...nel.org,
efectn@...tonmail.com,
krzk+dt@...nel.org,
conor+dt@...nel.org,
heiko@...ech.de,
nick@...das.com,
jagan@...eble.ai,
dsimic@...jaro.org,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Jacobe Zang <jacobe.zang@...ion.com>
Subject: [PATCH v2 2/5] net: wireless: brcmfmac: Add optional 32k clock enable support
WiFi modules often require 32kHz clock to function. Add support to
enable the clock to PCIe driver.
Co-developed-by: Ondrej Jirman <megi@....cz>
Signed-off-by: Ondrej Jirman <megi@....cz>
Signed-off-by: Jacobe Zang <jacobe.zang@...ion.com>
---
.../net/wireless/broadcom/brcm80211/brcmfmac/pcie.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
index 06698a714b523..4a7eb83a60ffc 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
@@ -3,6 +3,7 @@
* Copyright (c) 2014 Broadcom Corporation
*/
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/firmware.h>
@@ -2411,6 +2412,7 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
struct brcmf_pciedev *pcie_bus_dev;
struct brcmf_core *core;
struct brcmf_bus *bus;
+ struct clk *clk;
if (!id) {
id = pci_match_id(brcmf_pcie_devid_table, pdev);
@@ -2422,6 +2424,14 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
+ clk = devm_clk_get_optional_enabled(&pdev->dev, "32k");
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+ if (clk) {
+ brcmf_dbg(PCIE, "enabling 32kHz clock\n", pdev->vendor, pdev->device);
+ clk_set_rate(clk, 32768);
+ }
+
ret = -ENOMEM;
devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
if (devinfo == NULL)
--
2.34.1
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