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Message-ID: <CADrjBPoP_ZXyNrbS7vwVOqZTBqp3Brg7zigYukf-p1jX4AtHCg@mail.gmail.com>
Date: Mon, 24 Jun 2024 12:23:54 +0100
From: Peter Griffin <peter.griffin@...aro.org>
To: André Draszik <andre.draszik@...aro.org>
Cc: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Marek Szyprowski <m.szyprowski@...sung.com>, Sylwester Nawrocki <s.nawrocki@...sung.com>,
Alim Akhtar <alim.akhtar@...sung.com>, Sam Protsenko <semen.protsenko@...aro.org>,
Krzysztof Kozlowski <krzk@...nel.org>, Tudor Ambarus <tudor.ambarus@...aro.org>,
Will McVicker <willmcvicker@...gle.com>, Roy Luo <royluo@...gle.com>, kernel-team@...roid.com,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v3 4/6] phy: exynos5-usbdrd: convert (phy) register access
clock to clk_bulk
Hi André
On Mon, 17 Jun 2024 at 17:45, André Draszik <andre.draszik@...aro.org> wrote:
>
> In preparation for support for additional platforms, convert the phy
> register access clock to using the clk_bulk interfaces.
>
> Newer SoCs like Google Tensor gs101 require additional clocks for
> access to additional (different) register areas (PHY, PMA, PCS), and
> converting to clk_bulk simplifies addition of those extra clocks.
>
> Signed-off-by: André Draszik <andre.draszik@...aro.org>
>
> ---
Reviewed-by: Peter Griffin <peter.griffin@...aro.org>
and
Tested-by: Peter Griffin <peter.griffin@...aro.org>
Tested using my Pixel 6 pro device. USB comes up and it is possible to
use adb from the host computer to the phone.
regards,
Peter
[..]
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