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Message-ID: <Zns236F7vXPov4WK@x1>
Date: Tue, 25 Jun 2024 14:30:07 -0700
From: Drew Fustini <dfustini@...storrent.com>
To: Thomas Bonnefille <thomas.bonnefille@...tlin.com>
Cc: Andi Shyti <andi.shyti@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Jisheng Zhang <jszhang@...nel.org>, Guo Ren <guoren@...nel.org>,
Fu Wei <wefu@...hat.com>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
Conor Dooley <conor@...nel.org>,
Jarkko Nikula <jarkko.nikula@...ux.intel.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Paul Walmsley <paul.walmsley@...ive.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Miquèl Raynal <miquel.raynal@...tlin.com>,
linux-i2c@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v3 2/3] riscv: dts: thead: Add TH1520 I2C nodes
On Tue, Jun 18, 2024 at 09:42:39AM +0200, Thomas Bonnefille wrote:
> Add nodes for the six I2C on the T-Head TH1520 RISCV SoC.
>
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@...tlin.com>
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 60 +++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index d88d4cade02c..f0b2b05e9bd4 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -232,6 +232,36 @@ uart3: serial@...7f04000 {
> status = "disabled";
> };
>
> + i2c0: i2c@...7f20000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xe7f20000 0x0 0x4000>;
> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk CLK_I2C0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@...7f24000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xe7f24000 0x0 0x4000>;
> + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk CLK_I2C1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@...7f28000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xe7f28000 0x0 0x4000>;
> + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk CLK_I2C4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> gpio@...7f34000 {
> compatible = "snps,dw-apb-gpio";
> reg = <0xff 0xe7f34000 0x0 0x1000>;
> @@ -320,6 +350,16 @@ padctrl0_apsys: pinctrl@...c007000 {
> clocks = <&clk CLK_PADCTRL0>;
> };
>
> + i2c2: i2c@...c00c000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xec00c000 0x0 0x4000>;
> + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk CLK_I2C2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> uart2: serial@...c010000 {
> compatible = "snps,dw-apb-uart";
> reg = <0xff 0xec010000 0x0 0x4000>;
> @@ -331,6 +371,16 @@ uart2: serial@...c010000 {
> status = "disabled";
> };
>
> + i2c3: i2c@...c014000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xec014000 0x0 0x4000>;
> + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk CLK_I2C3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> dmac0: dma-controller@...fc00000 {
> compatible = "snps,axi-dma-1.01a";
> reg = <0xff 0xefc00000 0x0 0x1000>;
> @@ -405,6 +455,16 @@ uart5: serial@...7f0c000 {
> status = "disabled";
> };
>
> + i2c5: i2c@...7f2c000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xf7f2c000 0x0 0x4000>;
> + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk CLK_I2C5>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> timer4: timer@...fc33000 {
> compatible = "snps,dw-apb-timer";
> reg = <0xff 0xffc33000 0x0 0x14>;
>
> --
> 2.45.2
>
Reviewed-by: Drew Fustini <dfustini@...storrent.com>
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