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Message-ID: <73cb638e-4982-49a2-ba79-0e78402b59ad@quicinc.com>
Date: Tue, 25 Jun 2024 11:03:30 +0530
From: Gokul Sriram P <quic_gokulsri@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: <sboyd@...nel.org>, <andersson@...nel.org>, <bjorn.andersson@...aro.org>,
<david.brown@...aro.org>, <devicetree@...r.kernel.org>,
<jassisinghbrar@...il.com>, <linux-arm-msm@...r.kernel.org>,
<linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-remoteproc@...r.kernel.org>, <mark.rutland@....com>,
<mturquette@...libre.com>, <ohad@...ery.com>, <robh@...nel.org>,
<sricharan@...eaurora.org>, <gokulsri@...eaurora.org>
Subject: Re: [PATCH v9 1/8] remoteproc: qcom: Add PRNG proxy clock
On 6/22/2024 2:38 AM, Dmitry Baryshkov wrote:
> On Fri, Jun 21, 2024 at 05:16:52PM GMT, Gokul Sriram Palanisamy wrote:
>> PRNG clock is needed by the secure PIL, support for the same
>> is added in subsequent patches.
> Which 'same'?
> What is 'secure PIL'?
will elaborate in the updated version.
To answer your question, secure PIL is signed PIL image which only
TrustZone can authenticate and load.
>> Signed-off-by: Nikhil Prakash V <quic_nprakash@...cinc.com>
>> Signed-off-by: Sricharan R <quic_srichara@...cinc.com>
>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@...cinc.com>
>> ---
>> drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
>> 1 file changed, 47 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
>> index 94f68c919ee6..366b19cbd994 100644
>> --- a/drivers/remoteproc/qcom_q6v5_wcss.c
>> +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
>> @@ -91,19 +91,6 @@ enum {
>> WCSS_QCS404,
>> };
>>
>> -struct wcss_data {
>> - const char *firmware_name;
>> - unsigned int crash_reason_smem;
>> - u32 version;
>> - bool aon_reset_required;
>> - bool wcss_q6_reset_required;
>> - const char *ssr_name;
>> - const char *sysmon_name;
>> - int ssctl_id;
>> - const struct rproc_ops *ops;
>> - bool requires_force_stop;
>> -};
>> -
>> struct q6v5_wcss {
>> struct device *dev;
>>
>> @@ -128,6 +115,7 @@ struct q6v5_wcss {
>> struct clk *qdsp6ss_xo_cbcr;
>> struct clk *qdsp6ss_core_gfmux;
>> struct clk *lcc_bcr_sleep;
>> + struct clk *prng_clk;
>> struct regulator *cx_supply;
>> struct qcom_sysmon *sysmon;
>>
>> @@ -151,6 +139,21 @@ struct q6v5_wcss {
>> struct qcom_rproc_ssr ssr_subdev;
>> };
>>
>> +struct wcss_data {
>> + int (*init_clock)(struct q6v5_wcss *wcss);
>> + int (*init_regulator)(struct q6v5_wcss *wcss);
>> + const char *firmware_name;
>> + unsigned int crash_reason_smem;
>> + u32 version;
>> + bool aon_reset_required;
>> + bool wcss_q6_reset_required;
>> + const char *ssr_name;
>> + const char *sysmon_name;
>> + int ssctl_id;
>> + const struct rproc_ops *ops;
>> + bool requires_force_stop;
>> +};
> Move this back and use forward-declaration of struct q6v5_wcss.
sure. Will update.
>> +
>> static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
>> {
>> int ret;
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