linux-kernel - Re: [PATCH] perf/x86/amd: Warn only on new bits set

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Message-ID: <cc187abf-fbcc-4d4d-8764-faa9d1ceadd1@paulmck-laptop>
Date: Wed, 26 Jun 2024 06:47:10 -0700
From: "Paul E. McKenney" <paulmck@...nel.org>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Breno Leitao <leitao@...ian.org>, sandipan.das@....com,
	Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	Namhyung Kim <namhyung@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Jiri Olsa <jolsa@...nel.org>, Ian Rogers <irogers@...gle.com>,
	Adrian Hunter <adrian.hunter@...el.com>,
	"Liang, Kan" <kan.liang@...ux.intel.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Borislav Petkov <bp@...en8.de>,
	Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
	"H. Peter Anvin" <hpa@...or.com>, leit@...a.com,
	"open list:PERFORMANCE EVENTS SUBSYSTEM" <linux-perf-users@...r.kernel.org>,
	"open list:PERFORMANCE EVENTS SUBSYSTEM" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] perf/x86/amd: Warn only on new bits set

On Wed, Jun 26, 2024 at 10:51:53AM +0200, Peter Zijlstra wrote:
> On Tue, Jun 25, 2024 at 07:47:06AM -0700, Paul E. McKenney wrote:
> > On Tue, Jun 25, 2024 at 01:57:34PM +0200, Peter Zijlstra wrote:
> > > On Fri, May 24, 2024 at 07:10:20AM -0700, Breno Leitao wrote:
> > > > Warning at every leaking bits can cause a flood of message, triggering
> > > > vairous stall-warning mechanisms to fire, including CSD locks, which
> > > > makes the machine to be unusable.
> > > > 
> > > > Track the bits that are being leaked, and only warn when a new bit is
> > > > set.
> > > > 
> > > > Suggested-by: Paul E. McKenney <paulmck@...nel.org>
> > > > Signed-off-by: Breno Leitao <leitao@...ian.org>
> > > > ---
> > > >  arch/x86/events/amd/core.c | 9 +++++++--
> > > >  1 file changed, 7 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> > > > index 1fc4ce44e743..df0ba2382d13 100644
> > > > --- a/arch/x86/events/amd/core.c
> > > > +++ b/arch/x86/events/amd/core.c
> > > > @@ -941,11 +941,12 @@ static int amd_pmu_v2_snapshot_branch_stack(struct perf_branch_entry *entries, u
> > > >  static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
> > > >  {
> > > >  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> > > > +	static atomic64_t status_warned = ATOMIC64_INIT(0);
> > > > +	u64 reserved, status, mask, new_bits;
> > > >  	struct perf_sample_data data;
> > > >  	struct hw_perf_event *hwc;
> > > >  	struct perf_event *event;
> > > >  	int handled = 0, idx;
> > > > -	u64 reserved, status, mask;
> > > >  	bool pmu_enabled;
> > > >  
> > > >  	/*
> > > > @@ -1010,7 +1011,11 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
> > > >  	 * the corresponding PMCs are expected to be inactive according to the
> > > >  	 * active_mask
> > > >  	 */
> > > > -	WARN_ON(status > 0);
> > > > +	if (status > 0) {
> > > > +		new_bits = atomic64_fetch_or(status, &status_warned) ^ atomic64_read(&status_warned);
> > > > +		// A new bit was set for the very first time.
> > > > +		WARN(new_bits, "New overflows for inactive PMCs: %llx\n", new_bits);
> > > > +	}
> > > 
> > > Why not just a WARN_ON_ONCE() instead? This really shouldn't be
> > > happening in the first place.
> > 
> > We did consider that, but seeing the full set of bits that shouldn't
> > have been happening in the first place helps with debuggging.
> > 
> > But is there a better way to accumulate and print the full set of
> > unexpected bits?
> 
> Dunno, I was just wondering if the whole thing wasn't massive overkill.
> The changelog wasn't really explaining much here.

For me, the two additional executable lines of code seems to be a small
price to pay to be able to see all the bits, not just the first one that
happened to be set.

							Thanx, Paul