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Message-ID: <20240626185221.GC3104@kernel.org>
Date: Wed, 26 Jun 2024 19:52:21 +0100
From: Simon Horman <horms@...nel.org>
To: Sky Huang <SkyLake.Huang@...iatek.com>
Cc: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Daniel Golle <daniel@...rotopia.org>,
Qingfang Deng <dqfext@...il.com>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Steven Liu <Steven.Liu@...iatek.com>
Subject: Re: [PATCH net-next v9 11/13] net: phy: add driver for built-in 2.5G
ethernet PHY on MT7988
On Wed, Jun 26, 2024 at 06:43:27PM +0800, Sky Huang wrote:
> From: "SkyLake.Huang" <skylake.huang@...iatek.com>
>
> Add support for internal 2.5Gphy on MT7988. This driver will load
> necessary firmware, add appropriate time delay and figure out LED.
> Also, certain control registers will be set to fix link-up issues.
>
> Signed-off-by: SkyLake.Huang <skylake.huang@...iatek.com>
...
Hi Sky,
Sorry for not providing this review earlier in the process.
> diff --git a/drivers/net/phy/mediatek/mtk-2p5ge.c b/drivers/net/phy/mediatek/mtk-2p5ge.c
...
> +static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
> +{
> + struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
> + void __iomem *md32_en_cfg_base, *pmb_addr;
> + struct device *dev = &phydev->mdio.dev;
> + const struct firmware *fw;
> + int ret, i;
> + u16 reg;
> +
> + if (priv->fw_loaded)
> + return 0;
> +
> + pmb_addr = ioremap(MT7988_2P5GE_PMB_FW_BASE, MT7988_2P5GE_PMB_FW_LEN);
> + if (!pmb_addr)
> + return -ENOMEM;
> + md32_en_cfg_base = ioremap(MT7988_2P5GE_MD32_EN_CFG_BASE,
> + MT7988_2P5GE_MD32_EN_CFG_LEN);
> + if (!md32_en_cfg_base) {
> + ret = -ENOMEM;
> + goto free_pmb;
> + }
> +
> + ret = request_firmware(&fw, MT7988_2P5GE_PMB_FW, dev);
> + if (ret) {
> + dev_err(dev, "failed to load firmware: %s, ret: %d\n",
> + MT7988_2P5GE_PMB_FW, ret);
> + goto free;
> + }
> +
> + if (fw->size != MT7988_2P5GE_PMB_FW_SIZE) {
> + dev_err(dev, "Firmware size 0x%zx != 0x%x\n",
> + fw->size, MT7988_2P5GE_PMB_FW_SIZE);
> + ret = -EINVAL;
> + goto free;
It seems that this leaks any resources allocated by request_firmware():
I think a call to release_firmware() is needed in this unwind path.
Flagged by Smatch.
> + }
> +
> + reg = readw(md32_en_cfg_base);
> + if (reg & MD32_EN) {
> + phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
> + usleep_range(10000, 11000);
> + }
> + phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
> +
> + /* Write magic number to safely stall MCU */
> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
> +
> + for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4)
> + writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
> + release_firmware(fw);
> + dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n",
> + be16_to_cpu(*((__be16 *)(fw->data +
> + MT7988_2P5GE_PMB_FW_SIZE - 8))),
> + *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6),
> + *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5),
> + *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2),
> + *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1));
> +
> + writew(reg & ~MD32_EN, md32_en_cfg_base);
> + writew(reg | MD32_EN, md32_en_cfg_base);
> + phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
> + /* We need a delay here to stabilize initialization of MCU */
> + usleep_range(7000, 8000);
> + dev_info(dev, "Firmware loading/trigger ok.\n");
> +
> + priv->fw_loaded = true;
> +
> +free:
> + iounmap(md32_en_cfg_base);
> +free_pmb:
> + iounmap(pmb_addr);
> +
> + return ret ? ret : 0;
I'm feeling that I'm missing something incredibly obvious,
but could this simply be:
return ret;
> +}
...
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