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Message-Id: <20240626-misc_perf_fixes-v3-2-de3f8ed88dab@rivosinc.com>
Date: Wed, 26 Jun 2024 00:23:02 -0700
From: Atish Patra <atishp@...osinc.com>
To: linux-riscv@...ts.infradead.org, kvm-riscv@...ts.infradead.org
Cc: Atish Patra <atishp@...shpatra.org>, Anup Patel <anup@...infault.org>,
Will Deacon <will@...nel.org>, Mark Rutland <mark.rutland@....com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Andrew Jones <ajones@...tanamicro.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Samuel Holland <samuel.holland@...ive.com>,
Palmer Dabbelt <palmer@...osinc.com>,
Alexandre Ghiti <alexghiti@...osinc.com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
kvm@...r.kernel.org, Atish Patra <atishp@...osinc.com>
Subject: [PATCH v3 2/3] drivers/perf: riscv: Reset the counter to hpmevent
mapping while starting cpus
From: Samuel Holland <samuel.holland@...ive.com>
Currently, we stop all the counters while a new cpu is brought online.
However, the hpmevent to counter mappings are not reset. The firmware may
have some stale encoding in their mapping structure which may lead to
undesirable results. We have not encountered such scenario though.
Signed-off-by: Atish Patra <atishp@...osinc.com>
---
drivers/perf/riscv_pmu_sbi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index a2e4005e1fd0..94bc369a3454 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -762,7 +762,7 @@ static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
* which may include counters that are not enabled yet.
*/
sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
- 0, pmu->cmask, 0, 0, 0, 0);
+ 0, pmu->cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0);
}
static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu)
--
2.34.1
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