linux-kernel - [PATCH v3 3/7] dt-bindings: soc: intel: lgm-syscon: Move to dedicated schema

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Message-Id: <20240626-dt-bindings-mfd-syscon-split-v3-3-3409903bb99b@linaro.org>
Date: Wed, 26 Jun 2024 12:09:12 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Orson Zhai <orsonzhai@...il.com>, 
 Baolin Wang <baolin.wang@...ux.alibaba.com>, 
 Chunyan Zhang <zhang.lyra@...il.com>, Jacky Huang <ychuang3@...oton.com>, 
 Shan-Chun Hung <schung@...oton.com>, 
 Khuong Dinh <khuong@...amperecomputing.com>, Lee Jones <lee@...nel.org>, 
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Chuanhua Lei <lchuanhua@...linear.com>, 
 Rahul Tanwar <rtanwar@...linear.com>, 
 Lars Povlsen <lars.povlsen@...rochip.com>, 
 Steen Hegelund <Steen.Hegelund@...rochip.com>, 
 Daniel Machon <daniel.machon@...rochip.com>, UNGLinuxDriver@...rochip.com, 
 Nishanth Menon <nm@...com>, Matthias Brugger <matthias.bgg@...il.com>, 
 AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: Jiaxun Yang <jiaxun.yang@...goat.com>, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
 linux-mediatek@...ts.infradead.org, 
 Conor Dooley <conor.dooley@...rochip.com>, 
 Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, 
 Rahul Tanwar <rahul.tanwar@...ux.intel.com>, 
 Amireddy Mallikarjuna reddy <mallikarjunax.reddy@...el.com>, 
 "Zhu, Yi Xin" <Yixin.zhu@...el.com>
Subject: [PATCH v3 3/7] dt-bindings: soc: intel: lgm-syscon: Move to
 dedicated schema

intel,lgm-syscon is not a simple syscon device - it has children - thus
it should be fully documented in its own binding.

Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---

Context might depend on patch in Lee's MFD tree:
https://lore.kernel.org/all/171828959006.2643902.8308227314531523435.b4-ty@kernel.org/
and also further patches here depend on this one.

We need to cleanup intel's emails. Does this bounce?
Cc: Rahul Tanwar <rahul.tanwar@...ux.intel.com>
Cc: Amireddy Mallikarjuna reddy <mallikarjunax.reddy@...el.com>
Cc: "Zhu, Yi Xin" <Yixin.zhu@...el.com>
---
 Documentation/devicetree/bindings/mfd/syscon.yaml  |  1 -
 .../bindings/soc/intel/intel,lgm-syscon.yaml       | 57 ++++++++++++++++++++++
 2 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index af442767aa96..b9bf5bc05e92 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -77,7 +77,6 @@ properties:
               - hisilicon,pcie-sas-subctrl
               - hisilicon,peri-subctrl
               - hpe,gxp-sysreg
-              - intel,lgm-syscon
               - loongson,ls1b-syscon
               - loongson,ls1c-syscon
               - lsi,axxia-syscon
diff --git a/Documentation/devicetree/bindings/soc/intel/intel,lgm-syscon.yaml b/Documentation/devicetree/bindings/soc/intel/intel,lgm-syscon.yaml
new file mode 100644
index 000000000000..6951d55356d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/intel/intel,lgm-syscon.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/intel/intel,lgm-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightning Mountain(LGM) Syscon
+
+maintainers:
+  - Chuanhua Lei <lchuanhua@...linear.com>
+  - Rahul Tanwar <rtanwar@...linear.com>
+
+properties:
+  compatible:
+    items:
+      - const: intel,lgm-syscon
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  ranges: true
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+patternProperties:
+  "^emmc-phy@[0-9a-f]+$":
+    $ref: /schemas/phy/intel,lgm-emmc-phy.yaml#
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    chiptop@...00000 {
+        compatible = "intel,lgm-syscon", "syscon";
+        reg = <0xe0200000 0x100>;
+        ranges = <0x0 0xe0200000 0x100>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        emmc-phy@a8 {
+            compatible = "intel,lgm-emmc-phy";
+            reg = <0x00a8 0x10>;
+            clocks = <&emmc>;
+            #phy-cells = <0>;
+        };
+    };

-- 
2.43.0